From patchwork Tue Mar 25 11:36:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrylo Tkachov X-Patchwork-Id: 333396 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id ED07014008A for ; Tue, 25 Mar 2014 22:36:47 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=tXyM1A9PTFen+za9W0tWF4MVNsYUpVyokDy7vsjWldS rLaCh78lFfUyD6CRIKdLUs78gVF43Q7On8VYeQzTkJm7guUY92XHzcrWhNGiJCr9 P01b3r4CffzlnFd/nYEgVeFSIAXmG4DeatC+sOaXz6flPLZLHUaT55uRl4ahIkz4 = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=5estrJZirS+B2KyWaH3TscBRtAE=; b=mDWX548z+urSsm142 f2a7Ob2auPldTDISkhicO8Ssq2xKkKgQ/6lVgcSo9vHF6Ec12JS9WTHQe5UeaKeT 2Dx5hY+/io49Mo4fKGooj6UhjVO6FkF9uhftYdag2z+A3pMzyzLhNh1DtLn3LxSB xhGyGBg+sWsdKeY2sflJoL43K4= Received: (qmail 32532 invoked by alias); 25 Mar 2014 11:36:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 32520 invoked by uid 89); 25 Mar 2014 11:36:38 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 25 Mar 2014 11:36:36 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Tue, 25 Mar 2014 11:36:33 +0000 Received: from [10.1.208.24] ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 25 Mar 2014 11:36:46 +0000 Message-ID: <53316A3F.60000@arm.com> Date: Tue, 25 Mar 2014 11:36:31 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130804 Thunderbird/17.0.8 MIME-Version: 1.0 To: GCC Patches CC: Ramana Radhakrishnan , Richard Earnshaw Subject: [PATCH][ARM] Cortex-A8 rtx cost table X-MC-Unique: 114032511363306901 X-IsSubscribed: yes Hi all, This patch adds the rtx cost table for the Cortex-A8 core. It's an ARMv7 core, so it goes into arm.c instead of aarch-cost-tables.h. Bootstrapped and tested on a Cortex-A8 Linux system and benchmarked to make sure no performance regressions. There are various small improvements here and there. Ok for next stage 1? Thanks, Kyrill 2013-03-25 Kyrylo Tkachov * config/arm/arm.c (cortexa8_extra_costs): New table. (arm_cortex_a8_tune): New tuning struct. * config/arm/arm-cores.def (cortex-a8): Use cortex_a8 tuning struct. commit 82b5eadc7978c90f3a5f1daf2223ae83f3bc10f6 Author: Kyrylo Tkachov Date: Wed Feb 12 17:29:53 2014 +0000 Cortex-A8 costs diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index 3d9dfcd..6269338 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -136,7 +136,7 @@ ARM_CORE("cortex-m0plus", cortexm0plus, cortexm0plus, 6M, FL_LDSCHED, v6m) ARM_CORE("generic-armv7-a", genericv7a, genericv7a, 7A, FL_LDSCHED, cortex) ARM_CORE("cortex-a5", cortexa5, cortexa5, 7A, FL_LDSCHED, cortex_a5) ARM_CORE("cortex-a7", cortexa7, cortexa7, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a7) -ARM_CORE("cortex-a8", cortexa8, cortexa8, 7A, FL_LDSCHED, cortex) +ARM_CORE("cortex-a8", cortexa8, cortexa8, 7A, FL_LDSCHED, cortex_a8) ARM_CORE("cortex-a9", cortexa9, cortexa9, 7A, FL_LDSCHED, cortex_a9) ARM_CORE("cortex-a12", cortexa12, cortexa12, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a12) ARM_CORE("cortex-a15", cortexa15, cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index c65d84b..d01ecce 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1066,6 +1066,107 @@ const struct cpu_cost_table cortexa9_extra_costs = } }; +const struct cpu_cost_table cortexa8_extra_costs = +{ + /* ALU */ + { + 0, /* arith. */ + 0, /* logical. */ + COSTS_N_INSNS (1), /* shift. */ + 0, /* shift_reg. */ + COSTS_N_INSNS (1), /* arith_shift. */ + 0, /* arith_shift_reg. */ + COSTS_N_INSNS (1), /* log_shift. */ + 0, /* log_shift_reg. */ + 0, /* extend. */ + 0, /* extend_arith. */ + 0, /* bfi. */ + 0, /* bfx. */ + 0, /* clz. */ + 0, /* non_exec. */ + true /* non_exec_costs_exec. */ + }, + { + /* MULT SImode */ + { + COSTS_N_INSNS (1), /* simple. */ + COSTS_N_INSNS (1), /* flag_setting. */ + COSTS_N_INSNS (1), /* extend. */ + COSTS_N_INSNS (1), /* add. */ + COSTS_N_INSNS (1), /* extend_add. */ + COSTS_N_INSNS (30) /* idiv. No HW div on Cortex A8. */ + }, + /* MULT DImode */ + { + 0, /* simple (N/A). */ + 0, /* flag_setting (N/A). */ + COSTS_N_INSNS (2), /* extend. */ + 0, /* add (N/A). */ + COSTS_N_INSNS (2), /* extend_add. */ + 0 /* idiv (N/A). */ + } + }, + /* LD/ST */ + { + COSTS_N_INSNS (1), /* load. */ + COSTS_N_INSNS (1), /* load_sign_extend. */ + COSTS_N_INSNS (1), /* ldrd. */ + COSTS_N_INSNS (1), /* ldm_1st. */ + 1, /* ldm_regs_per_insn_1st. */ + 2, /* ldm_regs_per_insn_subsequent. */ + COSTS_N_INSNS (1), /* loadf. */ + COSTS_N_INSNS (1), /* loadd. */ + COSTS_N_INSNS (1), /* load_unaligned. */ + COSTS_N_INSNS (1), /* store. */ + COSTS_N_INSNS (1), /* strd. */ + COSTS_N_INSNS (1), /* stm_1st. */ + 1, /* stm_regs_per_insn_1st. */ + 2, /* stm_regs_per_insn_subsequent. */ + COSTS_N_INSNS (1), /* storef. */ + COSTS_N_INSNS (1), /* stored. */ + COSTS_N_INSNS (1) /* store_unaligned. */ + }, + { + /* FP SFmode */ + { + COSTS_N_INSNS (36), /* div. */ + COSTS_N_INSNS (11), /* mult. */ + COSTS_N_INSNS (20), /* mult_addsub. */ + COSTS_N_INSNS (30), /* fma. */ + COSTS_N_INSNS (9), /* addsub. */ + COSTS_N_INSNS (3), /* fpconst. */ + COSTS_N_INSNS (3), /* neg. */ + COSTS_N_INSNS (6), /* compare. */ + COSTS_N_INSNS (4), /* widen. */ + COSTS_N_INSNS (4), /* narrow. */ + COSTS_N_INSNS (8), /* toint. */ + COSTS_N_INSNS (8), /* fromint. */ + COSTS_N_INSNS (8) /* roundint. */ + }, + /* FP DFmode */ + { + COSTS_N_INSNS (64), /* div. */ + COSTS_N_INSNS (16), /* mult. */ + COSTS_N_INSNS (25), /* mult_addsub. */ + COSTS_N_INSNS (30), /* fma. */ + COSTS_N_INSNS (9), /* addsub. */ + COSTS_N_INSNS (3), /* fpconst. */ + COSTS_N_INSNS (3), /* neg. */ + COSTS_N_INSNS (6), /* compare. */ + COSTS_N_INSNS (6), /* widen. */ + COSTS_N_INSNS (6), /* narrow. */ + COSTS_N_INSNS (8), /* toint. */ + COSTS_N_INSNS (8), /* fromint. */ + COSTS_N_INSNS (8) /* roundint. */ + } + }, + /* Vector */ + { + COSTS_N_INSNS (1) /* alu. */ + } +}; + + const struct cpu_cost_table cortexa7_extra_costs = { @@ -1584,6 +1685,22 @@ const struct tune_params arm_cortex_tune = false /* Prefer Neon for 64-bits bitops. */ }; +const struct tune_params arm_cortex_a8_tune = +{ + arm_9e_rtx_costs, + &cortexa8_extra_costs, + NULL, /* Sched adj cost. */ + 1, /* Constant limit. */ + 5, /* Max cond insns. */ + ARM_PREFETCH_NOT_BENEFICIAL, + false, /* Prefer constant pool. */ + arm_default_branch_cost, + false, /* Prefer LDRD/STRD. */ + {true, true}, /* Prefer non short circuit. */ + &arm_default_vec_cost, /* Vectorizer costs. */ + false /* Prefer Neon for 64-bits bitops. */ +}; + const struct tune_params arm_cortex_a7_tune = { arm_9e_rtx_costs,