From patchwork Wed Mar 19 09:56:26 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrylo Tkachov X-Patchwork-Id: 331668 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 061882C0086 for ; Wed, 19 Mar 2014 20:57:09 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; q= dns; s=default; b=RZPt1XHHIwWq/z8Jx0uYWnPFCw4XQEVOTGh4qnDDrd0nwt gVw5uWewUCmxgrNj5eRAni+cB+5uJuuwVmRIHG9R422P918d4X/OJ6eRfTBlamuY lB2om1QS50C8I+kBQCXTERV15NjHj+LL7mJ1uXFlvFd7IAQCh718wrpkgGo/w= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; s= default; bh=fsh/1RzgOqTC6LDHgJdj3Vl0scA=; b=VK5m6kdYiVKCBqhH1FYv 6RJ5kfkNNqGrLzrH6pJm6pABlbRoE+sUlUcczf8iS1ldYjqaRGa3TCkrNx+Cr1mp qsajFKTP0Sprqex1Zw/JzTqq0rh7g27PwTLuhVB0f2D+RPCDRQ0m0K/+FrnYETCd 5Ki3e0ol3lAgJ54bKfCWEy4= Received: (qmail 19245 invoked by alias); 19 Mar 2014 09:57:01 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 19234 invoked by uid 89); 19 Mar 2014 09:57:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 19 Mar 2014 09:56:31 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Wed, 19 Mar 2014 09:56:29 +0000 Received: from [10.1.208.24] ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 19 Mar 2014 09:56:39 +0000 Message-ID: <532969CA.8020903@arm.com> Date: Wed, 19 Mar 2014 09:56:26 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130804 Thunderbird/17.0.8 MIME-Version: 1.0 To: GCC Patches , Ramana Radhakrishnan , Richard Earnshaw Subject: [PATCH][ARM][3/3] Recognise bitwise operations leading to SImode rev16 X-MC-Unique: 114031909562909801 X-IsSubscribed: yes Hi all, This is the arm equivalent of patch [2/3] in the series that adds combine patterns for the bitwise operations leading to a rev16 instruction. It reuses the functions that were put in aarch-common.c to properly cost these operations. I tried matching a DImode rev16 (with the intent of splitting it into two rev16 ops) like aarch64 but combine wouldn't try to match that bitwise pattern in DImode like aarch64 does. Instead it tries various exotic combinations with subregs. Tested arm-none-eabi, bootstrap on arm-none-linux-gnueabihf. Ok for stage1? [gcc/] 2014-03-19 Kyrylo Tkachov * config/arm/arm.md (arm_rev16si2): New pattern. (arm_rev16si2_alt): Likewise. * config/arm/arm.c (arm_new_rtx_costs): Handle rev16 case. [gcc/testsuite/] 2014-03-19 Kyrylo Tkachov * gcc.target/arm/rev16.c: New test. commit 04e60723bd1fa2f8e2adcfeed676390643ffec0c Author: Kyrylo Tkachov Date: Tue Feb 25 15:26:52 2014 +0000 [ARM] Implement SImode rev16 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 8d1d721..ed603f0 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -9716,8 +9716,17 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, /* Vector mode? */ *cost = LIBCALL_COST (2); return false; + case IOR: + if (mode == SImode && arm_arch6 && aarch_rev16_p (x)) + { + *cost = COSTS_N_INSNS (1); + if (speed_p) + *cost += extra_cost->alu.rev; - case AND: case XOR: case IOR: + return true; + } + /* Fall through. */ + case AND: case XOR: if (mode == SImode) { enum rtx_code subcode = GET_CODE (XEXP (x, 0)); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 4df24a2..47bc747 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12668,6 +12668,44 @@ (set_attr "type" "rev")] ) +;; There are no canonicalisation rules for the position of the lshiftrt, ashift +;; operations within an IOR/AND RTX, therefore we have two patterns matching +;; each valid permutation. + +(define_insn "arm_rev16si2" + [(set (match_operand:SI 0 "register_operand" "=l,l,r") + (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "l,l,r") + (const_int 8)) + (match_operand:SI 3 "const_int_operand" "n,n,n")) + (and:SI (lshiftrt:SI (match_dup 1) + (const_int 8)) + (match_operand:SI 2 "const_int_operand" "n,n,n"))))] + "arm_arch6 + && aarch_rev16_shleft_mask_imm_p (operands[3], SImode) + && aarch_rev16_shright_mask_imm_p (operands[2], SImode)" + "rev16\\t%0, %1" + [(set_attr "arch" "t1,t2,32") + (set_attr "length" "2,2,4") + (set_attr "type" "rev")] +) + +(define_insn "arm_rev16si2_alt" + [(set (match_operand:SI 0 "register_operand" "=l,l,r") + (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "l,l,r") + (const_int 8)) + (match_operand:SI 2 "const_int_operand" "n,n,n")) + (and:SI (ashift:SI (match_dup 1) + (const_int 8)) + (match_operand:SI 3 "const_int_operand" "n,n,n"))))] + "arm_arch6 + && aarch_rev16_shleft_mask_imm_p (operands[3], SImode) + && aarch_rev16_shright_mask_imm_p (operands[2], SImode)" + "rev16\\t%0, %1" + [(set_attr "arch" "t1,t2,32") + (set_attr "length" "2,2,4") + (set_attr "type" "rev")] +) + (define_expand "bswaphi2" [(set (match_operand:HI 0 "s_register_operand" "=r") (bswap:HI (match_operand:HI 1 "s_register_operand" "r")))] diff --git a/gcc/testsuite/gcc.target/arm/rev16.c b/gcc/testsuite/gcc.target/arm/rev16.c new file mode 100644 index 0000000..1c869b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/rev16.c @@ -0,0 +1,35 @@ +/* { dg-options "-O2" } */ +/* { dg-do run } */ + +extern void abort (void); + +typedef unsigned int __u32; + +__u32 +__rev16_32_alt (__u32 x) +{ + return (((__u32)(x) & (__u32)0xff00ff00UL) >> 8) + | (((__u32)(x) & (__u32)0x00ff00ffUL) << 8); +} + +__u32 +__rev16_32 (__u32 x) +{ + return (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) + | (((__u32)(x) & (__u32)0xff00ff00UL) >> 8); +} + +int +main (void) +{ + volatile __u32 in32 = 0x12345678; + volatile __u32 expected32 = 0x34127856; + + if (__rev16_32 (in32) != expected32) + abort (); + + if (__rev16_32_alt (in32) != expected32) + abort (); + + return 0; +}