From patchwork Wed Jul 19 03:06:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: HAO CHEN GUI X-Patchwork-Id: 1809565 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=ld05thvx; dkim-atps=neutral Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4R5LpS5RQ3z1yY1 for ; Wed, 19 Jul 2023 13:26:56 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5565C3855591 for ; Wed, 19 Jul 2023 03:26:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5565C3855591 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689737214; bh=Wc9hIy2RN6N0Uv+ap7h76QKAXiUG3W+a+5fzZetHwvQ=; h=Date:To:Subject:Cc:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=ld05thvxn5V8X+masMjneLV6XuzHUnoTuNsGZtfqD9YGV8OorfvX2b8RMfuGavhTo zbPHr2UKYcwF2ya10eyVSZmRc3lQlbpkLfy+1inQ1I+cZ4YPcQVBZVOMPN6xuY9bbW Yfw6UeV45U2hcxWwpj9646WUzUibPN66Z/WlB2HE= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 459DC3858C74 for ; Wed, 19 Jul 2023 03:26:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 459DC3858C74 Received: from pps.filterd (m0353723.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36J39O9J030522; Wed, 19 Jul 2023 03:26:33 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3rx6yngwg9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jul 2023 03:26:33 +0000 Received: from m0353723.ppops.net (m0353723.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 36J3CoQ6008160; Wed, 19 Jul 2023 03:26:32 GMT Received: from ppma13.dal12v.mail.ibm.com (dd.9e.1632.ip4.static.sl-reverse.com [50.22.158.221]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3rx6yngwft-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jul 2023 03:26:32 +0000 Received: from pps.filterd (ppma13.dal12v.mail.ibm.com [127.0.0.1]) by ppma13.dal12v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 36J2UENM007599; Wed, 19 Jul 2023 03:06:10 GMT Received: from smtprelay02.fra02v.mail.ibm.com ([9.218.2.226]) by ppma13.dal12v.mail.ibm.com (PPS) with ESMTPS id 3rv80j5au6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jul 2023 03:06:10 +0000 Received: from smtpav04.fra02v.mail.ibm.com (smtpav04.fra02v.mail.ibm.com [10.20.54.103]) by smtprelay02.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 36J367LN23659086 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 19 Jul 2023 03:06:07 GMT Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C41EF20040; Wed, 19 Jul 2023 03:06:07 +0000 (GMT) Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3F7F220043; Wed, 19 Jul 2023 03:06:06 +0000 (GMT) Received: from [9.200.144.106] (unknown [9.200.144.106]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 19 Jul 2023 03:06:05 +0000 (GMT) Message-ID: <531959dd-1342-cbf1-054b-faf620907aea@linux.ibm.com> Date: Wed, 19 Jul 2023 11:06:05 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Content-Language: en-US To: gcc-patches Subject: [PATCH-1, combine] Don't widen shift mode when target has rotate/mask instruction on original mode [PR93738] Cc: Segher Boessenkool , David , "Kewen.Lin" , Peter Bergner X-TM-AS-GCONF: 00 X-Proofpoint-GUID: KGp9MV6oQZkZXIdrjsrH-6Lu6R37SlFJ X-Proofpoint-ORIG-GUID: 2VMFDNLYcQ2ZYFWAXcq9LDHy6nedX7iE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-18_19,2023-07-18_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 spamscore=0 mlxlogscore=999 impostorscore=0 adultscore=0 priorityscore=1501 mlxscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307190027 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: HAO CHEN GUI via Gcc-patches From: HAO CHEN GUI Reply-To: HAO CHEN GUI Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi, The shift mode will be widen in combine pass if the operand has a normal subreg. But when the target already has rotate/mask/insert instructions on the narrow mode, it's unnecessary to widen the mode for lshiftrt. As the lshiftrt is commonly converted to rotate/mask insn, the widen mode blocks it to be further combined to rotate/mask/insert insn. The PR93738 shows the case. The lshiftrt:SI (subreg:SI (reg:DI)) is converted to subreg:SI (lshiftrt:DI (reg:DI)) and fails to match rotate/mask pattern. Trying 13, 10 -> 14: 13: r127:SI=r125:SI&0xfffffffffffff0ff REG_DEAD r125:SI 10: r124:SI=r129:DI#4 0>>0xc&0xf00 REG_DEAD r129:DI 14: r128:SI=r127:SI|r124:SI Failed to match this instruction: (set (reg:SI 128) (ior:SI (and:SI (reg:SI 125 [+-2 ]) (const_int -3841 [0xfffffffffffff0ff])) (and:SI (subreg:SI (zero_extract:DI (reg:DI 129) (const_int 32 [0x20]) (const_int 20 [0x14])) 4) (const_int 3840 [0xf00])))) Failed to match this instruction: (set (reg:SI 128) (ior:SI (and:SI (reg:SI 125 [+-2 ]) (const_int -3841 [0xfffffffffffff0ff])) (and:SI (subreg:SI (and:DI (lshiftrt:DI (reg:DI 129) (const_int 12 [0xc])) (const_int 4294967295 [0xffffffff])) 4) (const_int 3840 [0xf00])))) If not widen the shift mode, it can be combined to rotate/mask/insert insn as expected. Trying 13, 10 -> 14: 13: r127:SI=r125:SI&0xfffffffffffff0ff REG_DEAD r125:SI 10: r124:SI=r129:DI#4 0>>0xc&0xf00 REG_DEAD r129:DI 14: r128:SI=r127:SI|r124:SI REG_DEAD r127:SI REG_DEAD r124:SI Successfully matched this instruction: (set (reg:SI 128) (ior:SI (and:SI (reg:SI 125 [+-2 ]) (const_int -3841 [0xfffffffffffff0ff])) (and:SI (lshiftrt:SI (subreg:SI (reg:DI 129) 4) (const_int 12 [0xc])) (const_int 3840 [0xf00])))) This patch adds a target hook to indicate if rotate/mask instructions are supported on certain mode. If it's true, widen lshiftrt mode is skipped and shift is done on original mode. The patch fixes the regression of other rs6000 test cases. They're listed in the second patch. The patch passed regression test on Power Linux and x86 platforms. Thanks Gui Haochen ChangeLog combine: Not winden shift mode when target has rotate/mask instruction on original mode To winden shift mode is unnecessary when target already has rotate/mask instuctions on the original mode. It might blocks the further combine optimization on the original mode. For instance, further combine the insns to a rotate/mask/insert instruction on the original mode. This patch adds a hook to indicate if a target supports rotate/mask instructions on the certain mode. If it returns true, the widen shift mode will be skipped on lshiftrt. gcc/ PR target/93738 * combine.cc (try_widen_shift_mode): Skip to widen mode for lshiftrt when the target has rotate/mask instructions on original mode. * doc/tm.texi: Regenerate. * doc/tm.texi.in (TARGET_HAVE_ROTATE_AND_MASK): Add. * target.def (have_rotate_and_mask): New target hook. * targhooks.cc (default_have_rotate_and_mask): New function. * targhooks.h (default_have_rotate_and_mask): Declare. patch.diff diff --git a/gcc/combine.cc b/gcc/combine.cc index 304c020ec79..f22fe42931b 100644 --- a/gcc/combine.cc +++ b/gcc/combine.cc @@ -10475,20 +10475,25 @@ try_widen_shift_mode (enum rtx_code code, rtx op, int count, return orig_mode; case LSHIFTRT: - /* Similarly here but with zero bits. */ - if (HWI_COMPUTABLE_MODE_P (mode) - && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0) - return mode; - - /* We can also widen if the bits brought in will be masked off. This - operation is performed in ORIG_MODE. */ - if (outer_code == AND) + /* Skip wider mode when the target has rotate and mask instructions on + orig_mode. */ + if (!targetm.have_rotate_and_mask (orig_mode)) { - int care_bits = low_bitmask_len (orig_mode, outer_const); - - if (care_bits >= 0 - && GET_MODE_PRECISION (orig_mode) - care_bits >= count) + /* Similarly here but with zero bits. */ + if (HWI_COMPUTABLE_MODE_P (mode) + && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0) return mode; + + /* We can also widen if the bits brought in will be masked off. + This operation is performed in ORIG_MODE. */ + if (outer_code == AND) + { + int care_bits = low_bitmask_len (orig_mode, outer_const); + + if (care_bits >= 0 + && GET_MODE_PRECISION (orig_mode) - care_bits >= count) + return mode; + } } /* fall through */ diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 95ba56e05ae..cc7342b5253 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -11102,6 +11102,11 @@ The default is four for machines with a @code{casesi} instruction and five otherwise. This is best for most machines. @end deftypefn +@deftypefn {Target Hook} bool TARGET_HAVE_ROTATE_AND_MASK (machine_mode @var{mode}) +Return true if the target has rotate and mask instructions on mode + @var{mode}. +@end deftypefn + @defmac WORD_REGISTER_OPERATIONS Define this macro to 1 if operations between registers with integral mode smaller than a word are always performed on the entire register. To be diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index 4ac96dc357d..01257a7b3a2 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -7241,6 +7241,8 @@ is in effect. @hook TARGET_CASE_VALUES_THRESHOLD +@hook TARGET_HAVE_ROTATE_AND_MASK + @defmac WORD_REGISTER_OPERATIONS Define this macro to 1 if operations between registers with integral mode smaller than a word are always performed on the entire register. To be diff --git a/gcc/target.def b/gcc/target.def index 7d684296c17..ee2edfb4504 100644 --- a/gcc/target.def +++ b/gcc/target.def @@ -7169,6 +7169,15 @@ DEFHOOKPOD @option{-fsanitize=shadow-call-stack}. The default value is false.", bool, false) +/* Return true if the target has rotate and mask instructions for this\n\ + scalar integer mode. */ +DEFHOOK +(have_rotate_and_mask, + "Return true if the target has rotate and mask instructions on mode\n\ + @var{mode}.", + bool, (machine_mode mode), + default_have_rotate_and_mask) + /* Close the 'struct gcc_target' definition. */ HOOK_VECTOR_END (C90_EMPTY_HACK) diff --git a/gcc/targhooks.cc b/gcc/targhooks.cc index e190369f87a..4743aeb6d9a 100644 --- a/gcc/targhooks.cc +++ b/gcc/targhooks.cc @@ -2775,4 +2775,11 @@ default_gcov_type_size (void) return TYPE_PRECISION (long_long_integer_type_node) > 32 ? 64 : 32; } +bool +default_have_rotate_and_mask (machine_mode mode) +{ + gcc_assert (SCALAR_INT_MODE_P (mode)); + return false; +} + #include "gt-targhooks.h" diff --git a/gcc/targhooks.h b/gcc/targhooks.h index 1a0db8dddd5..209b7a3380b 100644 --- a/gcc/targhooks.h +++ b/gcc/targhooks.h @@ -303,4 +303,6 @@ extern rtx default_memtag_untagged_pointer (rtx, rtx); extern HOST_WIDE_INT default_gcov_type_size (void); +extern bool default_have_rotate_and_mask (machine_mode); + #endif /* GCC_TARGHOOKS_H */