diff mbox

[ARM] Add Cortex-A57 rtx costs table

Message ID 52EA5764.8000607@arm.com
State New
Headers show

Commit Message

Kyrylo Tkachov Jan. 30, 2014, 1:45 p.m. UTC 
Hi all,

This patch adds the rtx costs table for Cortex-A57 and sets its issue rate 
properly in the arm backend.

Tested on arm-none-eabi on a model.


Ok for trunk?

Thanks,
Kyrill

2014-01-30  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * config/arm/aarch-cost-tables.h (cortexa57_extra_costs): New table.
     Remove extra newline at end of file.
     * config/arm/arm.c (arm_cortex_a57_tune): New tuning struct.
     (arm_issue_rate): Handle cortexa57.
     * config/arm/arm-cores.def (cortex-a57): Use cortex_a57 tuning.
     (cortex-a57.cortex-a53): Likewise.

Comments

Ramana Radhakrishnan Feb. 6, 2014, 4:37 p.m. UTC | #1 
On Thu, Jan 30, 2014 at 1:45 PM, Kyrill Tkachov <kyrylo.tkachov@arm.com> wrote:
> Hi all,
>
> This patch adds the rtx costs table for Cortex-A57 and sets its issue rate
> properly in the arm backend.
>
> Tested on arm-none-eabi on a model.
>
>
> Ok for trunk?

In my view this is OK - this is just a tuning patch for A57 and we
should be able to take it now as it is not default anywhere and
unlikely to affect anyone doing bulk rebuilds.

However I would like an RM to ack this.

regards
Ramana

>
> Thanks,
> Kyrill
>
> 2014-01-30  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>
>     * config/arm/aarch-cost-tables.h (cortexa57_extra_costs): New table.
>     Remove extra newline at end of file.
>     * config/arm/arm.c (arm_cortex_a57_tune): New tuning struct.
>     (arm_issue_rate): Handle cortexa57.
>     * config/arm/arm-cores.def (cortex-a57): Use cortex_a57 tuning.
>     (cortex-a57.cortex-a53): Likewise.
Jakub Jelinek Feb. 6, 2014, 4:39 p.m. UTC | #2 
On Thu, Feb 06, 2014 at 04:37:38PM +0000, Ramana Radhakrishnan wrote:
> On Thu, Jan 30, 2014 at 1:45 PM, Kyrill Tkachov <kyrylo.tkachov@arm.com> wrote:
> > Hi all,
> >
> > This patch adds the rtx costs table for Cortex-A57 and sets its issue rate
> > properly in the arm backend.
> >
> > Tested on arm-none-eabi on a model.
> >
> >
> > Ok for trunk?
> 
> In my view this is OK - this is just a tuning patch for A57 and we
> should be able to take it now as it is not default anywhere and
> unlikely to affect anyone doing bulk rebuilds.
> 
> However I would like an RM to ack this.

Ok.

> > 2014-01-30  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
> >
> >     * config/arm/aarch-cost-tables.h (cortexa57_extra_costs): New table.
> >     Remove extra newline at end of file.
> >     * config/arm/arm.c (arm_cortex_a57_tune): New tuning struct.
> >     (arm_issue_rate): Handle cortexa57.
> >     * config/arm/arm-cores.def (cortex-a57): Use cortex_a57 tuning.
> >     (cortex-a57.cortex-a53): Likewise.

	Jakub
diff mbox

Patch

commit cb854a87cdee667d2042228600a221cffbef70ab
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Mon Jan 20 09:55:31 2014 +0000

    [ARM] a57 costs

diff --git a/gcc/config/arm/aarch-cost-tables.h b/gcc/config/arm/aarch-cost-tables.h
index 58addaf..c30ea2f 100644
--- a/gcc/config/arm/aarch-cost-tables.h
+++ b/gcc/config/arm/aarch-cost-tables.h
@@ -222,6 +222,104 @@  const struct cpu_cost_table cortexa53_extra_costs =
   }
 };
 
+const struct cpu_cost_table cortexa57_extra_costs =
+{
+  /* ALU */
+  {
+    0,                 /* arith.  */
+    0,                 /* logical.  */
+    0,                 /* shift.  */
+    COSTS_N_INSNS (1), /* shift_reg.  */
+    COSTS_N_INSNS (1), /* arith_shift.  */
+    COSTS_N_INSNS (1), /* arith_shift_reg.  */
+    COSTS_N_INSNS (1), /* log_shift.  */
+    COSTS_N_INSNS (1), /* log_shift_reg.  */
+    0,                 /* extend.  */
+    COSTS_N_INSNS (1), /* extend_arith.  */
+    COSTS_N_INSNS (1), /* bfi.  */
+    0,                 /* bfx.  */
+    0,                 /* clz.  */
+    0,                 /* non_exec.  */
+    true               /* non_exec_costs_exec.  */
+  },
+  {
+    /* MULT SImode */
+    {
+      COSTS_N_INSNS (2),       /* simple.  */
+      COSTS_N_INSNS (3),       /* flag_setting.  */
+      COSTS_N_INSNS (2),       /* extend.  */
+      COSTS_N_INSNS (2),       /* add.  */
+      COSTS_N_INSNS (2),       /* extend_add.  */
+      COSTS_N_INSNS (18)       /* idiv.  */
+    },
+    /* MULT DImode */
+    {
+      COSTS_N_INSNS (4),       /* simple.  */
+      0,                       /* flag_setting (N/A).  */
+      COSTS_N_INSNS (2),       /* extend.  */
+      COSTS_N_INSNS (4),       /* add.  */
+      COSTS_N_INSNS (2),       /* extend_add.  */
+      COSTS_N_INSNS (34)       /* idiv.  */
+    }
+  },
+  /* LD/ST */
+  {
+    COSTS_N_INSNS (3),         /* load.  */
+    COSTS_N_INSNS (3),         /* load_sign_extend.  */
+    COSTS_N_INSNS (3),         /* ldrd.  */
+    COSTS_N_INSNS (2),         /* ldm_1st.  */
+    1,                         /* ldm_regs_per_insn_1st.  */
+    2,                         /* ldm_regs_per_insn_subsequent.  */
+    COSTS_N_INSNS (4),         /* loadf.  */
+    COSTS_N_INSNS (4),         /* loadd.  */
+    COSTS_N_INSNS (5),         /* load_unaligned.  */
+    0,                         /* store.  */
+    0,                         /* strd.  */
+    0,                         /* stm_1st.  */
+    1,                         /* stm_regs_per_insn_1st.  */
+    2,                         /* stm_regs_per_insn_subsequent.  */
+    0,                         /* storef.  */
+    0,                         /* stored.  */
+    COSTS_N_INSNS (1)          /* store_unaligned.  */
+  },
+  {
+    /* FP SFmode */
+    {
+      COSTS_N_INSNS (17),      /* div.  */
+      COSTS_N_INSNS (5),       /* mult.  */
+      COSTS_N_INSNS (9),       /* mult_addsub. */
+      COSTS_N_INSNS (9),       /* fma.  */
+      COSTS_N_INSNS (4),       /* addsub.  */
+      COSTS_N_INSNS (2),       /* fpconst. */
+      COSTS_N_INSNS (2),       /* neg.  */
+      COSTS_N_INSNS (2),       /* compare.  */
+      COSTS_N_INSNS (4),       /* widen.  */
+      COSTS_N_INSNS (4),       /* narrow.  */
+      COSTS_N_INSNS (4),       /* toint.  */
+      COSTS_N_INSNS (4),       /* fromint.  */
+      COSTS_N_INSNS (4)        /* roundint.  */
+    },
+    /* FP DFmode */
+    {
+      COSTS_N_INSNS (31),      /* div.  */
+      COSTS_N_INSNS (5),       /* mult.  */
+      COSTS_N_INSNS (9),       /* mult_addsub.  */
+      COSTS_N_INSNS (9),       /* fma.  */
+      COSTS_N_INSNS (4),       /* addsub.  */
+      COSTS_N_INSNS (2),       /* fpconst.  */
+      COSTS_N_INSNS (2),       /* neg.  */
+      COSTS_N_INSNS (2),       /* compare.  */
+      COSTS_N_INSNS (4),       /* widen.  */
+      COSTS_N_INSNS (4),       /* narrow.  */
+      COSTS_N_INSNS (4),       /* toint.  */
+      COSTS_N_INSNS (4),       /* fromint.  */
+      COSTS_N_INSNS (4)        /* roundint.  */
+    }
+  },
+  /* Vector */
+  {
+    COSTS_N_INSNS (1)  /* alu.  */
+  }
+};
 
 #endif /* GCC_AARCH_COST_TABLES_H */
-
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 1e97273..42f00b4 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -153,7 +153,7 @@  ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,	7A,  FL_LDSCHED |
 
 /* V8 Architecture Processors */
 ARM_CORE("cortex-a53",	cortexa53, cortexa53,	8A, FL_LDSCHED | FL_CRC32, cortex_a53)
-ARM_CORE("cortex-a57",	cortexa57, cortexa15,	8A, FL_LDSCHED | FL_CRC32, cortex_a15)
+ARM_CORE("cortex-a57",	cortexa57, cortexa15,	8A, FL_LDSCHED | FL_CRC32, cortex_a57)
 
 /* V8 big.LITTLE implementations */
-ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A,  FL_LDSCHED | FL_CRC32, cortex_a15)
+ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A,  FL_LDSCHED | FL_CRC32, cortex_a57)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index f563c9d..de8b9b7 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -1632,6 +1632,22 @@  const struct tune_params arm_cortex_a53_tune =
   false						/* Prefer Neon for 64-bits bitops.  */
 };
 
+const struct tune_params arm_cortex_a57_tune =
+{
+  arm_9e_rtx_costs,
+  &cortexa57_extra_costs,
+  NULL,                                         /* Scheduler cost adjustment.  */
+  1,                                           /* Constant limit.  */
+  2,                                           /* Max cond insns.  */
+  ARM_PREFETCH_NOT_BENEFICIAL,
+  false,                                       /* Prefer constant pool.  */
+  arm_default_branch_cost,
+  true,                                       /* Prefer LDRD/STRD.  */
+  {true, true},                                /* Prefer non short circuit.  */
+  &arm_default_vec_cost,                       /* Vectorizer costs.  */
+  false                                        /* Prefer Neon for 64-bits bitops.  */
+};
+
 /* Branches can be dual-issued on Cortex-A5, so conditional execution is
    less appealing.  Set max_insns_skipped to a low value.  */
 
@@ -29331,6 +29347,7 @@  arm_issue_rate (void)
   switch (arm_tune)
     {
     case cortexa15:
+    case cortexa57:
       return 3;
 
     case cortexr4: