From patchwork Mon Jan 13 16:16:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom de Vries X-Patchwork-Id: 310228 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C63752C0091 for ; Tue, 14 Jan 2014 03:16:47 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; q=dns; s=default; b=rVw9EfyFDiTgJ5lVB KbUGhicc8c6ExpWh+Z+k0MP4BK1T5m8fgMXnzRQ7bVDdHyohXcm4A1/Hc/D33IhS WmL0/6KRq0wXWhKPCliZMyBl/6Y08Ery6/+dxUsAgnj3peRXgW1C8NujY7CkgnXa Lnijws5elQxlYGKNysBhxzmjs0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; s=default; bh=fmkkW4CO9FCDCDhvN72CDnS PDs8=; b=vXCuxS1ArpF840lUtfcpwE9idy/Kh4hFge3SQGD6MOVEYTV7uIQilRD +KckoDqc0J8hyGrOq5McB5WG54bOT3euu0It77DDxF9GUOexesmONk0XBtEI+E1D wzblXmJgogDAEXdWWB9BGyn1I+LNjpZzm3aOarxSdGZO24uaOQuI= Received: (qmail 20320 invoked by alias); 13 Jan 2014 16:16:40 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 20308 invoked by uid 89); 13 Jan 2014 16:16:39 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00 autolearn=ham version=3.3.2 X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 13 Jan 2014 16:16:38 +0000 Received: from svr-orw-exc-10.mgc.mentorg.com ([147.34.98.58]) by relay1.mentorg.com with esmtp id 1W2kBl-0003vL-KO from Tom_deVries@mentor.com ; Mon, 13 Jan 2014 08:16:33 -0800 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by SVR-ORW-EXC-10.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 13 Jan 2014 08:16:33 -0800 Received: from [127.0.0.1] (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server id 14.2.247.3; Mon, 13 Jan 2014 16:16:31 +0000 Message-ID: <52D4115E.2000904@mentor.com> Date: Mon, 13 Jan 2014 17:16:30 +0100 From: Tom de Vries User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 MIME-Version: 1.0 To: Richard Earnshaw CC: Vladimir Makarov , Richard Sandiford , Paolo Bonzini , "gcc-patches@gcc.gnu.org" Subject: Re: [PATCH][IRA] Analysis of register usage of functions for usage by IRA. References: <510282FE.1060809@mentor.com> <5102A694.5010000@redhat.com> <5113FC6B.7090702@mentor.com> <511C1538.308@redhat.com> <514199BC.9070608@mentor.com> <5141E8A1.5010203@redhat.com> <51558EF4.1030106@mentor.com> <51570E59.2020603@mentor.com> <52CEB533.50308@arm.com> <52CF099B.4070006@mentor.com> <52CFDBDF.7060105@arm.com> In-Reply-To: <52CFDBDF.7060105@arm.com> On 10-01-14 12:39, Richard Earnshaw wrote: >>> >>Consequently, you'll need to add a patch for AArch64 which has two >>> >>registers clobbered by PLT-based calls. >>> >> >> > >> >Thanks for pointing that out. That's r16 and r17, right? I can propose the hook >> >for AArch64, once we all agree on how the hook should look. >> > > Yes; and thanks! Hi Richard, I'm posting this patch that implements the TARGET_FN_OTHER_HARD_REG_USAGE hook for aarch64. It uses the conservative hook format for now. I've build gcc and cc1 with the patch, and observed the impact on this code snippet: ... static int bar (int x) { return x + 3; } int foo (int y) { return y + bar (y); } ... AFAICT, that looks as expected: ... $ gcc fuse-caller-save.c -mno-lra -fno-use-caller-save -O2 -S -o- > 1 $ gcc fuse-caller-save.c -mno-lra -fuse-caller-save -O2 -S -o- > 2 $ diff -u 1 2 ... Btw, the results are the same for -mno-lra and -mlra. I'm just using the -mno-lra version here because the -mlra version of -fuse-caller-save is still in review ( http://gcc.gnu.org/ml/gcc-patches/2013-12/msg00586.html ). Thanks, - Tom 2014-01-11 Tom de Vries * config/aarch64/aarch64.c (TARGET_FN_OTHER_HARD_REG_USAGE): Redefine as aarch64_fn_other_hard_reg_usage. (aarch64_fn_other_hard_reg_usage): New function. --- gcc/config/aarch64/aarch64.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 3b1f6b5..295fd5d 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -3287,6 +3287,16 @@ aarch64_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2) return true; } +/* Implement TARGET_FN_OTHER_HARD_REG_USAGE. */ + +static bool +aarch64_fn_other_hard_reg_usage (struct hard_reg_set_container *regs) +{ + SET_HARD_REG_BIT (regs->set, R16_REGNUM); + SET_HARD_REG_BIT (regs->set, R17_REGNUM); + return true; +} + enum machine_mode aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y) { @@ -8472,6 +8482,11 @@ aarch64_vectorize_vec_perm_const_ok (enum machine_mode vmode, #undef TARGET_FIXED_CONDITION_CODE_REGS #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs +#undef TARGET_FN_OTHER_HARD_REG_USAGE +#define TARGET_FN_OTHER_HARD_REG_USAGE \ + aarch64_fn_other_hard_reg_usage + + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-aarch64.h" -- 1.8.3.2