From patchwork Fri Dec 20 13:20:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chung-Ju Wu X-Patchwork-Id: 304030 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 684B22C01EE for ; Sat, 21 Dec 2013 00:20:27 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type :content-transfer-encoding; q=dns; s=default; b=gYyJRtyDdRCi7/zv U+lvvH6VM0CVTJwN0jtRW4Yh4aH0t6/UjN1PRpmZZPw2eJ31m1nWt8VkEhTjjzbm Nn0GYt/N73xE/2dPwRz/9mWd36D7UCHrzQFSq0LzELjJuMmeGUVgf6lBBPOXlXpr jONt2wrsEtRmeEXRIvaKIJjR9xU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type :content-transfer-encoding; s=default; bh=x8rG2zKJiAHZVuZxlQj2rt /JCr8=; b=gjuA5KNo43T5OTzKRxTwp2e+H+meubTJcHxzqDkQ/a8zSnXbM5CJSC lUxkyhDWZLe/XEYXQq6uYQS3pLkTKoEC/IQ5mJSqHlkEPg4xSLyf3ezB1O0K1j/h GOYDlH9FEy9KJq1PNDg7ayPKMcbdO1CKh5SypsZZKsdvrWVObjMw0= Received: (qmail 10040 invoked by alias); 20 Dec 2013 13:20:21 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 10027 invoked by uid 89); 20 Dec 2013 13:20:19 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.1 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-pd0-f171.google.com Received: from mail-pd0-f171.google.com (HELO mail-pd0-f171.google.com) (209.85.192.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Fri, 20 Dec 2013 13:20:18 +0000 Received: by mail-pd0-f171.google.com with SMTP id z10so2529515pdj.2 for ; Fri, 20 Dec 2013 05:20:16 -0800 (PST) X-Received: by 10.68.134.98 with SMTP id pj2mr8520706pbb.110.1387545616639; Fri, 20 Dec 2013 05:20:16 -0800 (PST) Received: from Wu-Chung-Jude-MacBook-Air.local (180-176-201-156.dynamic.kbronet.com.tw. [180.176.201.156]) by mx.google.com with ESMTPSA id at4sm14437156pbc.30.2013.12.20.05.20.11 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 20 Dec 2013 05:20:12 -0800 (PST) Message-ID: <52B44409.6020302@gmail.com> Date: Fri, 20 Dec 2013 21:20:09 +0800 From: Chung-Ju Wu User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.9; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 MIME-Version: 1.0 To: gcc-patches Subject: [PATCH, nds32] Committed: Fix inaccurate alignment checking when passing BLKmode argument. X-IsSubscribed: yes Hi, all, There is a problem in nds32.h to determine available register number for passing BLKmode argument. The original checking only refers to NDS32_NEED_N_REGS_FOR_ARG macro but that is not sufficient to make decision of using odd or even register number. It is supposed to further check the type alignment. We define a new macro NDS32_MODE_TYPE_ALIGN and rewrite NDS32_AVAILABLE_REGNUM_FOR_ARG definition. The patch for nds32.c and nds32.h is as follow: And the gcc/ChangeLog is as below: +2013-12-20 Chung-Ju Wu + + * config/nds32/nds32.h (NDS32_MODE_TYPE_ALIGN): New macro. + (NDS32_AVAILABLE_REGNUM_FOR_ARG): Use more accurate alignment checking + to determine available register number. + * config/nds32/nds32.c (nds32_needs_double_word_align): Use new + macro NDS32_MODE_TYPE_ALIGN. + (nds32_function_arg): Refine code layout. + 2013-12-19 Jeff Law * doc/invoke.texi: (dump-rtl-ree): Fix typo and clarify ree Bootstrapped and tested on nds32le-elf/nds32be-elf target. Committed as Rev.206142: http://gcc.gnu.org/r206142 Best regards, jasonwucj Index: gcc/config/nds32/nds32.h =================================================================== --- gcc/config/nds32/nds32.h (revision 206139) +++ gcc/config/nds32/nds32.h (working copy) @@ -126,6 +126,11 @@ #define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0) #define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0) +/* Get alignment according to mode or type information. + When 'type' is nonnull, there is no need to look at 'mode'. */ +#define NDS32_MODE_TYPE_ALIGN(mode, type) \ + (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode)) + /* Round X up to the nearest double word. */ #define NDS32_ROUND_UP_DOUBLE_WORD(value) (((value) + 7) & ~7) @@ -142,12 +147,18 @@ /* This macro is used to return the register number for passing argument. We need to obey the following rules: 1. If it is required MORE THAN one register, - make sure the register number is a even value. + we need to further check if it really needs to be + aligned on double words. + a) If double word alignment is necessary, + the register number must be even value. + b) Otherwise, the register number can be odd or even value. 2. If it is required ONLY one register, the register number can be odd or even value. */ -#define NDS32_AVAILABLE_REGNUM_FOR_ARG(reg_offset, mode, type) \ - ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \ - ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1) \ +#define NDS32_AVAILABLE_REGNUM_FOR_ARG(reg_offset, mode, type) \ + ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \ + ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY) \ + ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1) \ + : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM)) \ : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM)) /* This macro is to check if there are still available registers Index: gcc/config/nds32/nds32.c =================================================================== --- gcc/config/nds32/nds32.c (revision 206139) +++ gcc/config/nds32/nds32.c (working copy) @@ -1438,8 +1438,8 @@ { unsigned int align; - /* When 'type' is nonnull, there is no need to look at 'mode'. */ - align = (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode)); + /* Pick up the alignment according to the mode or type. */ + align = NDS32_MODE_TYPE_ALIGN (mode, type); return (align > PARM_BOUNDARY); } @@ -1853,10 +1853,10 @@ if (NDS32_ARG_PASS_IN_REG_P (cum->reg_offset, mode, type)) { /* Pick up the next available register number. */ - return gen_rtx_REG (mode, - NDS32_AVAILABLE_REGNUM_FOR_ARG (cum->reg_offset, - mode, - type)); + unsigned int regno; + + regno = NDS32_AVAILABLE_REGNUM_FOR_ARG (cum->reg_offset, mode, type); + return gen_rtx_REG (mode, regno); } else {