diff --git gcc/doc/extend.texi gcc/doc/extend.texi
index 151b7e9..25e8963 100644
--- gcc/doc/extend.texi
+++ gcc/doc/extend.texi
@@ -2502,6 +2502,12 @@ on data in the eight-bit data area.  Note the eight-bit data area is limited to
 You must use GAS and GLD from GNU binutils version 2.7 or later for
 this attribute to work correctly.
 
+@item exception
+@cindex exception handler functions
+Use this attribute on the NDS32 target to indicate that the specified function
+is an exception handler.  The compiler will generate corresponding sections
+for use in an exception handler.
+
 @item exception_handler
 @cindex exception handler functions on the Blackfin processor
 Use this attribute on the Blackfin to indicate that the specified function
@@ -2922,6 +2928,32 @@ void __attribute__ ((interrupt, use_shadow_register_set,
                      use_debug_exception_return)) v7 ();
 @end smallexample
 
+On NDS32 target, this attribute is to indicate that the specified function
+is an interrupt handler.  The compiler will generate corresponding sections
+for use in an interrupt handler.  You can use the following attributes
+to modify the behavior:
+@table @code
+@item nested
+@cindex @code{nested} attribute
+This interrupt service routine is interruptible.
+@item not_nested
+@cindex @code{not_nested} attribute
+This interrupt service routine is not interruptible.
+@item nested_ready
+@cindex @code{nested_ready} attribute
+This interrupt service routine is interruptible after @code{PSW.GIE}
+(global interrupt enable) is set.  This allows interrupt service routine to
+finish some short critical code before enabling interrupts.
+@item save_all
+@cindex @code{save_all} attribute
+The system will help save all registers into stack before entering
+interrupt handler.
+@item partial_save
+@cindex @code{partial_save} attribute
+The system will help save caller registers into stack before entering
+interrupt handler.
+@end table
+
 On RL78, use @code{brk_interrupt} instead of @code{interrupt} for
 handlers intended to be used with the @code{BRK} opcode (i.e.@: those
 that must end with @code{RETB} instead of @code{RETI}).
@@ -3143,10 +3175,11 @@ and newer.
 
 @item naked
 @cindex function without a prologue/epilogue code
-Use this attribute on the ARM, AVR, MCORE, RL78, RX and SPU ports to indicate that
-the specified function does not need prologue/epilogue sequences generated by
-the compiler.  It is up to the programmer to provide these sequences. The
-only statements that can be safely included in naked functions are
+Use this attribute on the ARM, AVR, MCORE, NDS32, RL78, RX and SPU ports
+to indicate that the specified function does not need prologue/epilogue
+sequences generated by the compiler.
+It is up to the programmer to provide these sequences.
+The only statements that can be safely included in naked functions are
 @code{asm} statements that do not have operands.  All other statements,
 including declarations of local variables, @code{if} statements, and so
 forth, should be avoided.  Naked functions should be used to implement the
@@ -3491,6 +3524,21 @@ safe since the loaders there save EAX, EDX and ECX.  (Lazy binding can be
 disabled with the linker or the loader if desired, to avoid the
 problem.)
 
+@item reset
+@cindex reset handler functions
+Use this attribute on the NDS32 target to indicate that the specified function
+is a reset handler.  The compiler will generate corresponding sections
+for use in a reset handler.  You can use the following attributes
+to provide extra exception handling:
+@table @code
+@item nmi
+@cindex @code{nmi} attribute
+Provide a user-defined function to handle NMI exception.
+@item warm
+@cindex @code{warm} attribute
+Provide a user-defined function to handle warm reset exception.
+@end table
+
 @item sseregparm
 @cindex @code{sseregparm} attribute
 On the Intel 386 with SSE support, the @code{sseregparm} attribute
@@ -8844,6 +8892,7 @@ instructions, but allow the compiler to schedule those calls.
 * MIPS Paired-Single Support::
 * MIPS Loongson Built-in Functions::
 * Other MIPS Built-in Functions::
+* NDS32 Built-in Functions::
 * picoChip Built-in Functions::
 * PowerPC Built-in Functions::
 * PowerPC AltiVec/VSX Built-in Functions::
@@ -11831,6 +11880,39 @@ GCC defines the preprocessor macro @code{___GCC_HAVE_BUILTIN_MIPS_CACHE}
 when this function is available.
 @end table
 
+@node NDS32 Built-in Functions
+@subsection NDS32 Built-in Functions
+
+These built-in functions are available for the NDS32 target:
+
+@table @code
+@item void __builtin_nds32_isync (int *@var{addr})
+Insert an ISYNC instruction into the instruction stream where
+@var{addr} is an instruction address for serialization.
+
+@item void __builtin_nds32_isb (void)
+Insert an ISB instruction into the instruction stream.
+
+@item int __builtin_nds32_mfsr (int @var{sr})
+Return the content of a system register which is mapped by @var{sr}.
+
+@item int __builtin_nds32_mfusr (int @var{usr})
+Return the content of a user space register which is mapped by @var{usr}.
+
+@item void __builtin_nds32_mtsr (int @var{value}, int @var{sr})
+Move the @var{value} to a system register which is mapped by @var{sr}.
+
+@item void __builtin_nds32_mtusr (int @var{value}, int @var{usr})
+Move the @var{value} to a user space register which is mapped by @var{usr}.
+
+@item void __builtin_nds32_setgie_en (void)
+Enable global interrupt.
+
+@item void __builtin_nds32_setgie_dis (void)
+Disable global interrupt.
+
+@end table
+
 @node picoChip Built-in Functions
 @subsection picoChip Built-in Functions
 
diff --git gcc/doc/install.texi gcc/doc/install.texi
index 8230625..f189f14 100644
--- gcc/doc/install.texi
+++ gcc/doc/install.texi
@@ -1849,6 +1849,11 @@ This option is only supported for the AVR target.  It is not supported for
 RTEMS configurations, which currently use newlib.  The option is
 supported since version 4.7.2 and is the default in 4.8.0 and newer.
 
+@item --with-nds32-lib=@var{library}
+Specifies that @var{library} setting is used for building @file{libgcc.a}.
+Currently, the valid @var{library} is 'newlib' or 'mculib'.
+This option is only supported for the NDS32 target.
+
 @item --with-build-time-tools=@var{dir}
 Specifies where to find the set of target tools (assembler, linker, etc.)
 that will be used while building GCC itself.  This option can be useful
diff --git gcc/doc/invoke.texi gcc/doc/invoke.texi
index 4995a5d..1e0231a 100644
--- gcc/doc/invoke.texi
+++ gcc/doc/invoke.texi
@@ -804,6 +804,20 @@ Objective-C and Objective-C++ Dialects}.
 @emph{Moxie Options}
 @gccoptlist{-meb -mel -mno-crt0}
 
+@emph{NDS32 Options}
+@gccoptlist{-mbig-endian -mlittle-endian @gol
+-mreduced-regs -mfull-regs @gol
+-mcmov -mno-cmov @gol
+-mperf-ext -mno-perf-ext @gol
+-mv3push -mno-v3push @gol
+-m16bit -mno-16bit @gol
+-mgp-direct -mno-gp-direct @gol
+-misr-vector-size=@var{num} @gol
+-mcache-block-size=@var{num} @gol
+-march=@var{arch} @gol
+-mforce-fp-as-gp -mforbid-fp-as-gp @gol
+-mex9 -mno-ctor-dtor}
+
 @emph{PDP-11 Options}
 @gccoptlist{-mfpu  -msoft-float  -mac0  -mno-ac0  -m40  -m45  -m10 @gol
 -mbcopy  -mbcopy-builtin  -mint32  -mno-int16 @gol
@@ -11028,6 +11042,7 @@ platform.
 * MMIX Options::
 * MN10300 Options::
 * Moxie Options::
+* NDS32 Options::
 * PDP-11 Options::
 * picoChip Options::
 * PowerPC Options::
@@ -17279,6 +17294,123 @@ Do not link in the C run-time initialization object file.
 
 @end table
 
+@node NDS32 Options
+@subsection NDS32 Options
+@cindex NDS32 Options
+
+These options are defined for NDS32 implementations:
+
+@table @gcctabopt
+
+@item -mbig-endian
+@opindex mbig-endian
+Generate code in big-endian mode.
+
+@item -mlittle-endian
+@opindex mlittle-endian
+Generate code in little-endian mode.
+
+@item -mreduced-regs
+@opindex mreduced-regs
+Use reduced-set registers for register allocation.
+
+@item -mfull-regs
+@opindex mfull-regs
+Use full-set registers for register allocation.
+
+@item -mcmov
+@opindex mcmov
+Generate conditional move instructions.
+
+@item -mno-cmov
+@opindex mno-cmov
+Do not generate conditional move instructions.
+
+@item -mperf-ext
+@opindex mperf-ext
+Generate performance extension instructions.
+
+@item -mno-perf-ext
+@opindex mno-perf-ext
+Do not generate performance extension instructions.
+
+@item -mv3push
+@opindex mv3push
+Generate v3 push25/pop25 instructions.
+
+@item -mno-v3push
+@opindex mno-v3push
+Do not generate v3 push25/pop25 instructions.
+
+@item -m16-bit
+@opindex m16-bit
+Generate 16-bit instructions.
+
+@item -mno-16-bit
+@opindex mno-16-bit
+Do not generate 16-bit instructions.
+
+@item -mgp-direct
+@opindex mgp-direct
+Generate GP base instructions directly.
+
+@item -mno-gp-direct
+@opindex mno-gp-direct
+Do no generate GP base instructions directly.
+
+@item -misr-vector-size=@var{num}
+@opindex misr-vector-size
+Specify the size of each vector for interrupt handler.
+The valid value is 4 or 16.
+
+@item -mcache-block-size=@var{num}
+@opindex mcache-block-size
+Specify the size of each cache block.  The size is the power of 2 in bytes.
+The valid value is: 4, 8, 16, 32, 64, 128, 256, or 512.
+
+@item -march=@var{arch}
+@opindex march
+Specify the name of the target architecture.
+The valid value is: v2, v3, or v3m.
+
+@item -mfp-as-gp
+@opindex mfp-as-gp
+Use special directives and code generation to guide linker doing
+fp-as-gp optimization.  Note that this is link time optimization,
+so make sure you pass @option{--relax} option to linker at linking stage.
+If you use gcc to invoke linker, issue the option @option{-Wl,--relax}.
+
+@item -mforce-fp-as-gp
+@opindex mforce-fp-as-gp
+Prevent $fp being allocated during register allocation so that compiler is able
+to force using $fp to access static and global variables for code-size reduction.
+Then compiler will use special directives and code generation to guide linker
+doing fp-as-gp optimization.
+Note that this is link time optimization,
+so make sure you pass @option{--relax} option to linker at linking stage.
+If you use gcc to invoke linker, issue the option @option{-Wl,--relax}.
+
+@item -mforbid-fp-as-gp
+@opindex mforbid-fp-as-gp
+Forbid using $fp to access static and global variables.
+This option strictly forbids fp-as-gp optimization
+regardless of @option{-mforce-fp-as-gp}.
+
+@item -mex9
+@opindex mex9
+Use special directives to guide linker doing ex9 optimization.
+Note that this is link time optimization,
+so make sure you pass @option{--relax} and @option{--mex9} option
+to linker at linking stage.
+If you use gcc to invoke linker,
+issue the option @option{-Wl,--relax -Wl,--mex9}.
+
+@item -mno-ctor-dtor
+@opindex mno-ctor-dtor
+Disable constructor/destructor feature.
+
+@end table
+
 @node PDP-11 Options
 @subsection PDP-11 Options
 @cindex PDP-11 Options
diff --git gcc/doc/md.texi gcc/doc/md.texi
index 04f76fe..e6b427d 100644
--- gcc/doc/md.texi
+++ gcc/doc/md.texi
@@ -3063,6 +3063,83 @@ A constant in the range of 0 to @minus{}255.
 
 @end table
 
+@item NDS32---@file{config/nds32/constraints.md}
+@table @code
+@item w
+LOW register class $r0 to $r7 constraint for V3 ISA.
+@item l
+LOW register class $r0 to $r7.
+@item d
+MIDDLE register class $r0 to $r11, $r16 to $r19.
+@item h
+HIGH register class $r12 to $r14, $r20 to $r31.
+@item t
+Temporary assist register $ta (i.e.@: $r15).
+@item k
+Stack register $sp.
+@item Iu03
+Unsigned immediate 3-bit value.
+@item Iu04
+Unsigned immediate 4-bit value.
+@item Is05
+Signed immediate 5-bit value.
+@item Iu05
+Unsigned immediate 5-bit value.
+@item Ip05
+Unsigned immediate 5-bit value for movpi45 instruction with range 16--47.
+@item Iu06
+Unsigned immediate 6-bit value constraint for addri36.sp instruction.
+@item Iu08
+Unsigned immediate 8-bit value.
+@item Iu09
+Unsigned immediate 9-bit value.
+@item Is10
+Signed immediate 10-bit value.
+@item Is11
+Signed immediate 11-bit value.
+@item Is15
+Signed immediate 15-bit value.
+@item Iu15
+Unsigned immediate 15-bit value.
+@item Ic15
+A constant which is not in the range of imm15u but ok for bclr instruction.
+@item Ie15
+A constant which is not in the range of imm15u but ok for bset instruction.
+@item It15
+A constant which is not in the range of imm15u but ok for btgl instruction.
+@item Ii15
+A constant whose compliment value is in the range of imm15u
+and ok for bitci instruction.
+@item Is16
+Signed immediate 16-bit value.
+@item Is17
+Signed immediate 17-bit value.
+@item Is19
+Signed immediate 19-bit value.
+@item Is20
+Signed immediate 20-bit value.
+@item Ispl
+The immediate value that need to be split.
+@item Ihig
+The immediate value that can be simply set high 20-bit.
+@item Izeb
+The immediate value 0xff.
+@item Ixls
+The immediate value 0x01.
+@item Ix11
+The immediate value 0x7ff.
+@item Ibms
+The immediate value with power of 2.
+@item Ifex
+The immediate value with power of 2 minus 1.
+@item U33
+Memory constraint for 333 format.
+@item U45
+Memory constraint for 45 format.
+@item U37
+Memory constraint for 37 format.
+@end table
+
 @item PDP-11---@file{config/pdp11/constraints.md}
 @table @code
 @item a
