From patchwork Wed Sep 11 11:36:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 1983905 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X3dnk3dR2z1y1S for ; Wed, 11 Sep 2024 21:36:42 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9E0D93858C32 for ; Wed, 11 Sep 2024 11:36:40 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgjp3.qq.com (smtpbgjp3.qq.com [54.92.39.34]) by sourceware.org (Postfix) with ESMTPS id B4EF03858C98 for ; Wed, 11 Sep 2024 11:36:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B4EF03858C98 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B4EF03858C98 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.92.39.34 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1726054580; cv=none; b=ChURjpNSGFDXF1EeffnLT2QBiJ0SfVPLgdPDVVzKxWoA3Cg4mvkpgPeMHQcnQWRUtLvdq+9lsQLjyBarHJS1XvJL4CPzhiQkvASQb5IjNn+3+03ZA+2sRnqbde2vl9yX/z6fbiYvrfzHt3iNuV7ItvdD6yHvYyIgIYDilHh0XDQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1726054580; c=relaxed/simple; bh=W8Da4hPW/8djZYHVjT5lK/srHwWlKjvtWrZkeJKWzZc=; h=Date:From:To:Subject:Mime-Version:Message-ID; b=L4FsSDwgVKf2xZ/hMjw1eBtC7jE1TZEvRaFssvnBNI15xWJs2acfx9ndZfZoxud5wL2KG8ytRKhYGwnjw7N1tSDdDSY8hSft6erZm8EtWD5fd1uJaPZkD11TVpFJIjleUZA9DD5DFrBfQT5fcwlT70R9xPXsFPfXR2MLWz8BYRI= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtpsz12t1726054571tds58b X-QQ-Originating-IP: xudPahotj62W8Z+3gV9SXrjt3QN833eCOBCymi5ApCk= Received: from LAPTOP-JJ6AJQDJ ( [14.155.59.50]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 11 Sep 2024 19:36:09 +0800 (CST) X-QQ-SSF: 0001000000000000000000000000000 X-QQ-GoodBg: 2 X-BIZMAIL-ID: 2217316702118022298 Date: Wed, 11 Sep 2024 19:36:10 +0800 From: =?utf-8?b?6ZKf5bGF5ZOy?= To: gcc-patches Cc: pan2.li , "Robin Dapp" , jeffreyalaw , kito.cheng Subject: [PATCH 1/2] RISC-V: Fix vl_used_by_non_rvv_insn logic of vsetvl pass References: <57a7c534-fc53-4391-ad93-052916710080.garthlei@linux.alibaba.com>, X-Priority: 3 X-GUID: CB4B4C10-8CDE-4811-A3DA-524019B8C4C5 X-Has-Attach: no X-Mailer: Foxmail 7.2.25.306[cn] Mime-Version: 1.0 Message-ID: <51AE84BB9E509EBC+202409111936098703655@rivai.ai> X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtpsz:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, HTML_MESSAGE, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, garthlei. Thanks for fixing it. I see, you are trying to fix this bug: lui a5,%hi(.LANCHOR0) addi a5,a5,%lo(.LANCHOR0) vsetivli zero,2,e8,mf8,ta,ma ---> It should be a4, 2 instead of zero, 2 vle64.v v1,0(a5) --- missing vsetvli a4, a4 here slli a4,a4,1 vsetvli zero,a4,e32,m1,ta,ma li a2,-1 addi a5,a5,16 vslide1down.vx v1,v1,a2 vslide1down.vx v1,v1,zero vsetivli zero,2,e64,m1,ta,ma vse64.v v1,0(a5) ret When I revisit the codes here: m_vl = ::get_vl ... update_avl -> "m_vl" variable is modified ... using wrong m_vl in the following. A dedicated temporary variable dest_vl looks reasonable here. LGTM. The RISC-V folks will commit this patch for you. Thanks. juzhe.zhong@rivai.ai From: Li, Pan2 Date: 2024-09-11 19:29 To: juzhe.zhong@rivai.ai Subject: FW: [PATCH 1/2] RISC-V: Fix vl_used_by_non_rvv_insn logic of vsetvl pass FYI. -----Original Message----- From: garthlei Sent: Wednesday, September 11, 2024 5:10 PM To: gcc-patches Subject: [PATCH 1/2] RISC-V: Fix vl_used_by_non_rvv_insn logic of vsetvl pass This patch fixes a bug in the current vsetvl pass. The current pass uses `m_vl` to determine whether the dest operand has been used by non-RVV instructions. However, `m_vl` may have been modified as a result of an `update_avl` call, and thus would be no longer the dest operand of the original instruction. This can lead to incorrect vsetvl eliminations, as is shown in the testcase. In this patch, we create a `dest_vl` variable for this scenerio. gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc: Use `dest_vl` for dest VL operand gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/vsetvl_bug-3.c: New test. --- gcc/config/riscv/riscv-vsetvl.cc | 16 +++++++++++----- .../gcc.target/riscv/rvv/vsetvl/vsetvl_bug-3.c | 17 +++++++++++++++++ 2 files changed, 28 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-3.c diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 017efa8bc17..ce831685439 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -1002,6 +1002,9 @@ public: void parse_insn (insn_info *insn) { + /* The VL dest of the insn */ + rtx dest_vl = NULL_RTX; + m_insn = insn; m_bb = insn->bb (); /* Return if it is debug insn for the consistency with optimize == 0. */ @@ -1035,7 +1038,10 @@ public: if (m_avl) { if (vsetvl_insn_p (insn->rtl ()) || has_vlmax_avl ()) - m_vl = ::get_vl (insn->rtl ()); + { + m_vl = ::get_vl (insn->rtl ()); + dest_vl = m_vl; + } if (has_nonvlmax_reg_avl ()) m_avl_def = find_access (insn->uses (), REGNO (m_avl))->def (); @@ -1132,22 +1138,22 @@ public: } /* Determine if dest operand(vl) has been used by non-RVV instructions. */ - if (has_vl ()) + if (dest_vl) { const hash_set vl_uses - = get_all_real_uses (get_insn (), REGNO (get_vl ())); + = get_all_real_uses (get_insn (), REGNO (dest_vl)); for (use_info *use : vl_uses) { gcc_assert (use->insn ()->is_real ()); rtx_insn *rinsn = use->insn ()->rtl (); if (!has_vl_op (rinsn) - || count_regno_occurrences (rinsn, REGNO (get_vl ())) != 1) + || count_regno_occurrences (rinsn, REGNO (dest_vl)) != 1) { m_vl_used_by_non_rvv_insn = true; break; } rtx avl = ::get_avl (rinsn); - if (!avl || !REG_P (avl) || REGNO (get_vl ()) != REGNO (avl)) + if (!avl || !REG_P (avl) || REGNO (dest_vl) != REGNO (avl)) { m_vl_used_by_non_rvv_insn = true; break; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-3.c new file mode 100644 index 00000000000..c155f5613d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-3.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O2 -fdump-rtl-vsetvl-details" } */ + +#include + +uint64_t a[2], b[2]; + +void +foo () +{ + size_t vl = __riscv_vsetvl_e64m1 (2); + vuint64m1_t vx = __riscv_vle64_v_u64m1 (a, vl); + vx = __riscv_vslide1down_vx_u64m1 (vx, 0xffffffffull, vl); + __riscv_vse64_v_u64m1 (b, vx, vl); +} + +/* { dg-final { scan-rtl-dump-not "Eliminate insn" "vsetvl" } } */