diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h
index da9d273..0e45b23 100644
--- a/gcc/config/arm/arm-cpu-data.h
+++ b/gcc/config/arm/arm-cpu-data.h
@@ -20,7 +20,7 @@
    License along with GCC; see the file COPYING3.  If not see
    <http://www.gnu.org/licenses/>.  */
 
-static const struct cpu_option cpu_opttab_arm9e[] = {
+static const cpu_arch_extension cpu_opttab_arm9e[] = {
   {
     "nofp", true,
     { ISA_ALL_FP, isa_nobit }
@@ -28,7 +28,7 @@ static const struct cpu_option cpu_opttab_arm9e[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_arm946es[] = {
+static const cpu_arch_extension cpu_opttab_arm946es[] = {
   {
     "nofp", true,
     { ISA_ALL_FP, isa_nobit }
@@ -36,7 +36,7 @@ static const struct cpu_option cpu_opttab_arm946es[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_arm966es[] = {
+static const cpu_arch_extension cpu_opttab_arm966es[] = {
   {
     "nofp", true,
     { ISA_ALL_FP, isa_nobit }
@@ -44,7 +44,7 @@ static const struct cpu_option cpu_opttab_arm966es[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_arm968es[] = {
+static const cpu_arch_extension cpu_opttab_arm968es[] = {
   {
     "nofp", true,
     { ISA_ALL_FP, isa_nobit }
@@ -52,7 +52,7 @@ static const struct cpu_option cpu_opttab_arm968es[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_arm10e[] = {
+static const cpu_arch_extension cpu_opttab_arm10e[] = {
   {
     "nofp", true,
     { ISA_ALL_FP, isa_nobit }
@@ -60,7 +60,7 @@ static const struct cpu_option cpu_opttab_arm10e[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_arm1020e[] = {
+static const cpu_arch_extension cpu_opttab_arm1020e[] = {
   {
     "nofp", true,
     { ISA_ALL_FP, isa_nobit }
@@ -68,7 +68,7 @@ static const struct cpu_option cpu_opttab_arm1020e[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_arm1022e[] = {
+static const cpu_arch_extension cpu_opttab_arm1022e[] = {
   {
     "nofp", true,
     { ISA_ALL_FP, isa_nobit }
@@ -76,7 +76,7 @@ static const struct cpu_option cpu_opttab_arm1022e[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_arm926ejs[] = {
+static const cpu_arch_extension cpu_opttab_arm926ejs[] = {
   {
     "nofp", true,
     { ISA_ALL_FP, isa_nobit }
@@ -84,7 +84,7 @@ static const struct cpu_option cpu_opttab_arm926ejs[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_arm1026ejs[] = {
+static const cpu_arch_extension cpu_opttab_arm1026ejs[] = {
   {
     "nofp", true,
     { ISA_ALL_FP, isa_nobit }
@@ -92,7 +92,7 @@ static const struct cpu_option cpu_opttab_arm1026ejs[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_genericv7a[] = {
+static const cpu_arch_extension cpu_opttab_genericv7a[] = {
   {
     "simd", false,
     { ISA_VFPv3,ISA_NEON, isa_nobit }
@@ -148,7 +148,7 @@ static const struct cpu_option cpu_opttab_genericv7a[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexa5[] = {
+static const cpu_arch_extension cpu_opttab_cortexa5[] = {
   {
     "nosimd", true,
     { ISA_ALL_SIMD, isa_nobit }
@@ -160,7 +160,7 @@ static const struct cpu_option cpu_opttab_cortexa5[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexa7[] = {
+static const cpu_arch_extension cpu_opttab_cortexa7[] = {
   {
     "nosimd", true,
     { ISA_ALL_SIMD, isa_nobit }
@@ -172,7 +172,7 @@ static const struct cpu_option cpu_opttab_cortexa7[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexa8[] = {
+static const cpu_arch_extension cpu_opttab_cortexa8[] = {
   {
     "nofp", true,
     { ISA_ALL_FP, isa_nobit }
@@ -180,7 +180,7 @@ static const struct cpu_option cpu_opttab_cortexa8[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexa9[] = {
+static const cpu_arch_extension cpu_opttab_cortexa9[] = {
   {
     "nofp", true,
     { ISA_ALL_FP, isa_nobit }
@@ -192,7 +192,7 @@ static const struct cpu_option cpu_opttab_cortexa9[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexa12[] = {
+static const cpu_arch_extension cpu_opttab_cortexa12[] = {
   {
     "nofp", true,
     { ISA_ALL_FP, isa_nobit }
@@ -200,7 +200,7 @@ static const struct cpu_option cpu_opttab_cortexa12[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexa15[] = {
+static const cpu_arch_extension cpu_opttab_cortexa15[] = {
   {
     "nofp", true,
     { ISA_ALL_FP, isa_nobit }
@@ -208,7 +208,7 @@ static const struct cpu_option cpu_opttab_cortexa15[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexa17[] = {
+static const cpu_arch_extension cpu_opttab_cortexa17[] = {
   {
     "nofp", true,
     { ISA_ALL_FP, isa_nobit }
@@ -216,7 +216,7 @@ static const struct cpu_option cpu_opttab_cortexa17[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexr5[] = {
+static const cpu_arch_extension cpu_opttab_cortexr5[] = {
   {
     "nofp.dp", true,
     { ISA_FP_DBL, isa_nobit }
@@ -228,7 +228,7 @@ static const struct cpu_option cpu_opttab_cortexr5[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexr7[] = {
+static const cpu_arch_extension cpu_opttab_cortexr7[] = {
   {
     "nofp", true,
     { ISA_ALL_FP, isa_nobit }
@@ -236,7 +236,7 @@ static const struct cpu_option cpu_opttab_cortexr7[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexr8[] = {
+static const cpu_arch_extension cpu_opttab_cortexr8[] = {
   {
     "nofp", true,
     { ISA_ALL_FP, isa_nobit }
@@ -244,7 +244,7 @@ static const struct cpu_option cpu_opttab_cortexr8[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexm7[] = {
+static const cpu_arch_extension cpu_opttab_cortexm7[] = {
   {
     "nofp.dp", true,
     { ISA_FP_DBL, isa_nobit }
@@ -256,7 +256,7 @@ static const struct cpu_option cpu_opttab_cortexm7[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexm4[] = {
+static const cpu_arch_extension cpu_opttab_cortexm4[] = {
   {
     "nofp", true,
     { ISA_ALL_FP, isa_nobit }
@@ -264,7 +264,7 @@ static const struct cpu_option cpu_opttab_cortexm4[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexa15cortexa7[] = {
+static const cpu_arch_extension cpu_opttab_cortexa15cortexa7[] = {
   {
     "nofp", true,
     { ISA_ALL_FP, isa_nobit }
@@ -272,7 +272,7 @@ static const struct cpu_option cpu_opttab_cortexa15cortexa7[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexa17cortexa7[] = {
+static const cpu_arch_extension cpu_opttab_cortexa17cortexa7[] = {
   {
     "nofp", true,
     { ISA_ALL_FP, isa_nobit }
@@ -280,7 +280,7 @@ static const struct cpu_option cpu_opttab_cortexa17cortexa7[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexa32[] = {
+static const cpu_arch_extension cpu_opttab_cortexa32[] = {
   {
     "crypto", false,
     { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
@@ -292,7 +292,7 @@ static const struct cpu_option cpu_opttab_cortexa32[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexa35[] = {
+static const cpu_arch_extension cpu_opttab_cortexa35[] = {
   {
     "crypto", false,
     { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
@@ -304,7 +304,7 @@ static const struct cpu_option cpu_opttab_cortexa35[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexa53[] = {
+static const cpu_arch_extension cpu_opttab_cortexa53[] = {
   {
     "crypto", false,
     { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
@@ -316,7 +316,7 @@ static const struct cpu_option cpu_opttab_cortexa53[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexa57[] = {
+static const cpu_arch_extension cpu_opttab_cortexa57[] = {
   {
     "crypto", false,
     { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
@@ -324,7 +324,7 @@ static const struct cpu_option cpu_opttab_cortexa57[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexa72[] = {
+static const cpu_arch_extension cpu_opttab_cortexa72[] = {
   {
     "crypto", false,
     { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
@@ -332,7 +332,7 @@ static const struct cpu_option cpu_opttab_cortexa72[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexa73[] = {
+static const cpu_arch_extension cpu_opttab_cortexa73[] = {
   {
     "crypto", false,
     { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
@@ -340,7 +340,7 @@ static const struct cpu_option cpu_opttab_cortexa73[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_exynosm1[] = {
+static const cpu_arch_extension cpu_opttab_exynosm1[] = {
   {
     "crypto", false,
     { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
@@ -348,7 +348,7 @@ static const struct cpu_option cpu_opttab_exynosm1[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_falkor[] = {
+static const cpu_arch_extension cpu_opttab_falkor[] = {
   {
     "crypto", false,
     { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
@@ -356,7 +356,7 @@ static const struct cpu_option cpu_opttab_falkor[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_qdf24xx[] = {
+static const cpu_arch_extension cpu_opttab_qdf24xx[] = {
   {
     "crypto", false,
     { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
@@ -364,7 +364,7 @@ static const struct cpu_option cpu_opttab_qdf24xx[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_xgene1[] = {
+static const cpu_arch_extension cpu_opttab_xgene1[] = {
   {
     "crypto", false,
     { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
@@ -372,7 +372,7 @@ static const struct cpu_option cpu_opttab_xgene1[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexa57cortexa53[] = {
+static const cpu_arch_extension cpu_opttab_cortexa57cortexa53[] = {
   {
     "crypto", false,
     { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
@@ -380,7 +380,7 @@ static const struct cpu_option cpu_opttab_cortexa57cortexa53[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexa72cortexa53[] = {
+static const cpu_arch_extension cpu_opttab_cortexa72cortexa53[] = {
   {
     "crypto", false,
     { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
@@ -388,7 +388,7 @@ static const struct cpu_option cpu_opttab_cortexa72cortexa53[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexa73cortexa35[] = {
+static const cpu_arch_extension cpu_opttab_cortexa73cortexa35[] = {
   {
     "crypto", false,
     { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
@@ -396,7 +396,7 @@ static const struct cpu_option cpu_opttab_cortexa73cortexa35[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexa73cortexa53[] = {
+static const cpu_arch_extension cpu_opttab_cortexa73cortexa53[] = {
   {
     "crypto", false,
     { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
@@ -404,7 +404,7 @@ static const struct cpu_option cpu_opttab_cortexa73cortexa53[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option cpu_opttab_cortexm33[] = {
+static const cpu_arch_extension cpu_opttab_cortexm33[] = {
   {
     "nofp", true,
     { ISA_ALL_FP, isa_nobit }
@@ -412,1396 +412,1839 @@ static const struct cpu_option cpu_opttab_cortexm33[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct processors all_cores[] =
+static const cpu_option all_cores[] =
 {
   {
-    "arm2",
-    TARGET_CPU_arm2,
-    (TF_CO_PROC | TF_NO_MODE32),
-    "2", BASE_ARCH_2,
     {
-      ISA_ARMv2,isa_bit_mode26,
-      isa_nobit
+      "arm2",
+      NULL,
+      {
+        ISA_ARMv2,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_slowmul_tune
+    TARGET_ARCH_armv2
   },
   {
-    "arm250",
-    TARGET_CPU_arm250,
-    (TF_CO_PROC | TF_NO_MODE32),
-    "2", BASE_ARCH_2,
     {
-      ISA_ARMv2,isa_bit_mode26,
-      isa_nobit
+      "arm250",
+      NULL,
+      {
+        ISA_ARMv2,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_slowmul_tune
+    TARGET_ARCH_armv2
   },
   {
-    "arm3",
-    TARGET_CPU_arm3,
-    (TF_CO_PROC | TF_NO_MODE32),
-    "2", BASE_ARCH_2,
     {
-      ISA_ARMv2,isa_bit_mode26,
-      isa_nobit
+      "arm3",
+      NULL,
+      {
+        ISA_ARMv2,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_slowmul_tune
+    TARGET_ARCH_armv2
   },
   {
-    "arm6",
-    TARGET_CPU_arm6,
-    (TF_CO_PROC),
-    "3", BASE_ARCH_3,
     {
-      ISA_ARMv3,isa_bit_mode26,
-      isa_nobit
+      "arm6",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_slowmul_tune
+    TARGET_ARCH_armv3
   },
   {
-    "arm60",
-    TARGET_CPU_arm60,
-    (TF_CO_PROC),
-    "3", BASE_ARCH_3,
     {
-      ISA_ARMv3,isa_bit_mode26,
-      isa_nobit
+      "arm60",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_slowmul_tune
+    TARGET_ARCH_armv3
   },
   {
-    "arm600",
-    TARGET_CPU_arm600,
-    (TF_CO_PROC | TF_WBUF),
-    "3", BASE_ARCH_3,
     {
-      ISA_ARMv3,isa_bit_mode26,
-      isa_nobit
+      "arm600",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_slowmul_tune
+    TARGET_ARCH_armv3
   },
   {
-    "arm610",
-    TARGET_CPU_arm610,
-    (TF_WBUF),
-    "3", BASE_ARCH_3,
     {
-      ISA_ARMv3,isa_bit_mode26,
-      isa_nobit
+      "arm610",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_slowmul_tune
+    TARGET_ARCH_armv3
   },
   {
-    "arm620",
-    TARGET_CPU_arm620,
-    (TF_CO_PROC | TF_WBUF),
-    "3", BASE_ARCH_3,
     {
-      ISA_ARMv3,isa_bit_mode26,
-      isa_nobit
+      "arm620",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_slowmul_tune
+    TARGET_ARCH_armv3
   },
   {
-    "arm7",
-    TARGET_CPU_arm7,
-    (TF_CO_PROC),
-    "3", BASE_ARCH_3,
     {
-      ISA_ARMv3,isa_bit_mode26,
-      isa_nobit
+      "arm7",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_slowmul_tune
+    TARGET_ARCH_armv3
   },
   {
-    "arm7d",
-    TARGET_CPU_arm7d,
-    (TF_CO_PROC),
-    "3", BASE_ARCH_3,
     {
-      ISA_ARMv3,isa_bit_mode26,
-      isa_nobit
+      "arm7d",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_slowmul_tune
+    TARGET_ARCH_armv3
   },
   {
-    "arm7di",
-    TARGET_CPU_arm7di,
-    (TF_CO_PROC),
-    "3", BASE_ARCH_3,
     {
-      ISA_ARMv3,isa_bit_mode26,
-      isa_nobit
+      "arm7di",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_slowmul_tune
+    TARGET_ARCH_armv3
   },
   {
-    "arm70",
-    TARGET_CPU_arm70,
-    (TF_CO_PROC),
-    "3", BASE_ARCH_3,
     {
-      ISA_ARMv3,isa_bit_mode26,
-      isa_nobit
+      "arm70",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_slowmul_tune
+    TARGET_ARCH_armv3
   },
   {
-    "arm700",
-    TARGET_CPU_arm700,
-    (TF_CO_PROC | TF_WBUF),
-    "3", BASE_ARCH_3,
     {
-      ISA_ARMv3,isa_bit_mode26,
-      isa_nobit
+      "arm700",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_slowmul_tune
+    TARGET_ARCH_armv3
   },
   {
-    "arm700i",
-    TARGET_CPU_arm700i,
-    (TF_CO_PROC | TF_WBUF),
-    "3", BASE_ARCH_3,
     {
-      ISA_ARMv3,isa_bit_mode26,
-      isa_nobit
+      "arm700i",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_slowmul_tune
+    TARGET_ARCH_armv3
   },
   {
-    "arm710",
-    TARGET_CPU_arm710,
-    (TF_WBUF),
-    "3", BASE_ARCH_3,
     {
-      ISA_ARMv3,isa_bit_mode26,
-      isa_nobit
+      "arm710",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_slowmul_tune
+    TARGET_ARCH_armv3
   },
   {
-    "arm720",
-    TARGET_CPU_arm720,
-    (TF_WBUF),
-    "3", BASE_ARCH_3,
     {
-      ISA_ARMv3,isa_bit_mode26,
-      isa_nobit
+      "arm720",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_slowmul_tune
+    TARGET_ARCH_armv3
   },
   {
-    "arm710c",
-    TARGET_CPU_arm710c,
-    (TF_WBUF),
-    "3", BASE_ARCH_3,
     {
-      ISA_ARMv3,isa_bit_mode26,
-      isa_nobit
+      "arm710c",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_slowmul_tune
+    TARGET_ARCH_armv3
   },
   {
-    "arm7100",
-    TARGET_CPU_arm7100,
-    (TF_WBUF),
-    "3", BASE_ARCH_3,
     {
-      ISA_ARMv3,isa_bit_mode26,
-      isa_nobit
+      "arm7100",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_slowmul_tune
+    TARGET_ARCH_armv3
   },
   {
-    "arm7500",
-    TARGET_CPU_arm7500,
-    (TF_WBUF),
-    "3", BASE_ARCH_3,
     {
-      ISA_ARMv3,isa_bit_mode26,
-      isa_nobit
+      "arm7500",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_slowmul_tune
+    TARGET_ARCH_armv3
   },
   {
-    "arm7500fe",
-    TARGET_CPU_arm7500fe,
-    (TF_CO_PROC | TF_WBUF),
-    "3", BASE_ARCH_3,
     {
-      ISA_ARMv3,isa_bit_mode26,
-      isa_nobit
+      "arm7500fe",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_slowmul_tune
+    TARGET_ARCH_armv3
   },
   {
-    "arm7m",
-    TARGET_CPU_arm7m,
-    (TF_CO_PROC),
-    "3M", BASE_ARCH_3M,
     {
-      ISA_ARMv3m,isa_bit_mode26,
-      isa_nobit
+      "arm7m",
+      NULL,
+      {
+        ISA_ARMv3m,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv3m
   },
   {
-    "arm7dm",
-    TARGET_CPU_arm7dm,
-    (TF_CO_PROC),
-    "3M", BASE_ARCH_3M,
     {
-      ISA_ARMv3m,isa_bit_mode26,
-      isa_nobit
+      "arm7dm",
+      NULL,
+      {
+        ISA_ARMv3m,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv3m
   },
   {
-    "arm7dmi",
-    TARGET_CPU_arm7dmi,
-    (TF_CO_PROC),
-    "3M", BASE_ARCH_3M,
     {
-      ISA_ARMv3m,isa_bit_mode26,
-      isa_nobit
+      "arm7dmi",
+      NULL,
+      {
+        ISA_ARMv3m,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv3m
   },
   {
-    "arm8",
-    TARGET_CPU_arm8,
-    (TF_LDSCHED),
-    "4", BASE_ARCH_4,
     {
-      ISA_ARMv4,isa_bit_mode26,
-      isa_nobit
+      "arm8",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv4
   },
   {
-    "arm810",
-    TARGET_CPU_arm810,
-    (TF_LDSCHED),
-    "4", BASE_ARCH_4,
     {
-      ISA_ARMv4,isa_bit_mode26,
-      isa_nobit
+      "arm810",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv4
   },
   {
-    "strongarm",
-    TARGET_CPU_strongarm,
-    (TF_LDSCHED | TF_STRONG),
-    "4", BASE_ARCH_4,
     {
-      ISA_ARMv4,isa_bit_mode26,
-      isa_nobit
+      "strongarm",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_strongarm_tune
+    TARGET_ARCH_armv4
   },
   {
-    "strongarm110",
-    TARGET_CPU_strongarm110,
-    (TF_LDSCHED | TF_STRONG),
-    "4", BASE_ARCH_4,
     {
-      ISA_ARMv4,isa_bit_mode26,
-      isa_nobit
+      "strongarm110",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_strongarm_tune
+    TARGET_ARCH_armv4
   },
   {
-    "strongarm1100",
-    TARGET_CPU_strongarm1100,
-    (TF_LDSCHED | TF_STRONG),
-    "4", BASE_ARCH_4,
     {
-      ISA_ARMv4,isa_bit_mode26,
-      isa_nobit
+      "strongarm1100",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_strongarm_tune
+    TARGET_ARCH_armv4
   },
   {
-    "strongarm1110",
-    TARGET_CPU_strongarm1110,
-    (TF_LDSCHED | TF_STRONG),
-    "4", BASE_ARCH_4,
     {
-      ISA_ARMv4,isa_bit_mode26,
-      isa_nobit
+      "strongarm1110",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_strongarm_tune
+    TARGET_ARCH_armv4
   },
   {
-    "fa526",
-    TARGET_CPU_fa526,
-    (TF_LDSCHED),
-    "4", BASE_ARCH_4,
     {
-      ISA_ARMv4,isa_bit_mode26,
-      isa_nobit
+      "fa526",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv4
   },
   {
-    "fa626",
-    TARGET_CPU_fa626,
-    (TF_LDSCHED),
-    "4", BASE_ARCH_4,
     {
-      ISA_ARMv4,isa_bit_mode26,
-      isa_nobit
+      "fa626",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv4
   },
   {
-    "arm7tdmi",
-    TARGET_CPU_arm7tdmi,
-    (TF_CO_PROC),
-    "4T", BASE_ARCH_4T,
     {
-      ISA_ARMv4t,
-      isa_nobit
+      "arm7tdmi",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv4t
   },
   {
-    "arm7tdmi-s",
-    TARGET_CPU_arm7tdmis,
-    (TF_CO_PROC),
-    "4T", BASE_ARCH_4T,
     {
-      ISA_ARMv4t,
-      isa_nobit
+      "arm7tdmi-s",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv4t
   },
   {
-    "arm710t",
-    TARGET_CPU_arm710t,
-    (TF_WBUF),
-    "4T", BASE_ARCH_4T,
     {
-      ISA_ARMv4t,
-      isa_nobit
+      "arm710t",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv4t
   },
   {
-    "arm720t",
-    TARGET_CPU_arm720t,
-    (TF_WBUF),
-    "4T", BASE_ARCH_4T,
     {
-      ISA_ARMv4t,
-      isa_nobit
+      "arm720t",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv4t
   },
   {
-    "arm740t",
-    TARGET_CPU_arm740t,
-    (TF_WBUF),
-    "4T", BASE_ARCH_4T,
     {
-      ISA_ARMv4t,
-      isa_nobit
+      "arm740t",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv4t
   },
   {
-    "arm9",
-    TARGET_CPU_arm9,
-    (TF_LDSCHED),
-    "4T", BASE_ARCH_4T,
     {
-      ISA_ARMv4t,
-      isa_nobit
+      "arm9",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv4t
   },
   {
-    "arm9tdmi",
-    TARGET_CPU_arm9tdmi,
-    (TF_LDSCHED),
-    "4T", BASE_ARCH_4T,
     {
-      ISA_ARMv4t,
-      isa_nobit
+      "arm9tdmi",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv4t
   },
   {
-    "arm920",
-    TARGET_CPU_arm920,
-    (TF_LDSCHED),
-    "4T", BASE_ARCH_4T,
     {
-      ISA_ARMv4t,
-      isa_nobit
+      "arm920",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv4t
   },
   {
-    "arm920t",
-    TARGET_CPU_arm920t,
-    (TF_LDSCHED),
-    "4T", BASE_ARCH_4T,
     {
-      ISA_ARMv4t,
-      isa_nobit
+      "arm920t",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv4t
   },
   {
-    "arm922t",
-    TARGET_CPU_arm922t,
-    (TF_LDSCHED),
-    "4T", BASE_ARCH_4T,
     {
-      ISA_ARMv4t,
-      isa_nobit
+      "arm922t",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv4t
   },
   {
-    "arm940t",
-    TARGET_CPU_arm940t,
-    (TF_LDSCHED),
-    "4T", BASE_ARCH_4T,
     {
-      ISA_ARMv4t,
-      isa_nobit
+      "arm940t",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv4t
   },
   {
-    "ep9312",
-    TARGET_CPU_ep9312,
-    (TF_LDSCHED),
-    "4T", BASE_ARCH_4T,
     {
-      ISA_ARMv4t,
-      isa_nobit
+      "ep9312",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv4t
   },
   {
-    "arm10tdmi",
-    TARGET_CPU_arm10tdmi,
-    (TF_LDSCHED),
-    "5T", BASE_ARCH_5T,
     {
-      ISA_ARMv5t,
-      isa_nobit
+      "arm10tdmi",
+      NULL,
+      {
+        ISA_ARMv5t,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv5t
   },
   {
-    "arm1020t",
-    TARGET_CPU_arm1020t,
-    (TF_LDSCHED),
-    "5T", BASE_ARCH_5T,
     {
-      ISA_ARMv5t,
-      isa_nobit
+      "arm1020t",
+      NULL,
+      {
+        ISA_ARMv5t,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv5t
   },
   {
-    "arm9e",
-    TARGET_CPU_arm9e,
-    (TF_LDSCHED),
-    "5TE", BASE_ARCH_5TE,
     {
-      ISA_ARMv5te,
-      ISA_VFPv2,ISA_FP_DBL,
-      isa_nobit
+      "arm9e",
+      cpu_opttab_arm9e,
+      {
+        ISA_ARMv5te,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
     },
-    cpu_opttab_arm9e,
-    &arm_9e_tune
+    TARGET_ARCH_armv5te
   },
   {
-    "arm946e-s",
-    TARGET_CPU_arm946es,
-    (TF_LDSCHED),
-    "5TE", BASE_ARCH_5TE,
     {
-      ISA_ARMv5te,
-      ISA_VFPv2,ISA_FP_DBL,
-      isa_nobit
+      "arm946e-s",
+      cpu_opttab_arm946es,
+      {
+        ISA_ARMv5te,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
     },
-    cpu_opttab_arm946es,
-    &arm_9e_tune
+    TARGET_ARCH_armv5te
   },
   {
-    "arm966e-s",
-    TARGET_CPU_arm966es,
-    (TF_LDSCHED),
-    "5TE", BASE_ARCH_5TE,
     {
-      ISA_ARMv5te,
-      ISA_VFPv2,ISA_FP_DBL,
-      isa_nobit
+      "arm966e-s",
+      cpu_opttab_arm966es,
+      {
+        ISA_ARMv5te,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
     },
-    cpu_opttab_arm966es,
-    &arm_9e_tune
+    TARGET_ARCH_armv5te
   },
   {
-    "arm968e-s",
-    TARGET_CPU_arm968es,
-    (TF_LDSCHED),
-    "5TE", BASE_ARCH_5TE,
     {
-      ISA_ARMv5te,
-      ISA_VFPv2,ISA_FP_DBL,
-      isa_nobit
+      "arm968e-s",
+      cpu_opttab_arm968es,
+      {
+        ISA_ARMv5te,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
     },
-    cpu_opttab_arm968es,
-    &arm_9e_tune
+    TARGET_ARCH_armv5te
   },
   {
-    "arm10e",
-    TARGET_CPU_arm10e,
-    (TF_LDSCHED),
-    "5TE", BASE_ARCH_5TE,
     {
-      ISA_ARMv5te,
-      ISA_VFPv2,ISA_FP_DBL,
-      isa_nobit
+      "arm10e",
+      cpu_opttab_arm10e,
+      {
+        ISA_ARMv5te,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
     },
-    cpu_opttab_arm10e,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv5te
   },
   {
-    "arm1020e",
-    TARGET_CPU_arm1020e,
-    (TF_LDSCHED),
-    "5TE", BASE_ARCH_5TE,
     {
-      ISA_ARMv5te,
-      ISA_VFPv2,ISA_FP_DBL,
-      isa_nobit
+      "arm1020e",
+      cpu_opttab_arm1020e,
+      {
+        ISA_ARMv5te,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
     },
-    cpu_opttab_arm1020e,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv5te
   },
   {
-    "arm1022e",
-    TARGET_CPU_arm1022e,
-    (TF_LDSCHED),
-    "5TE", BASE_ARCH_5TE,
     {
-      ISA_ARMv5te,
-      ISA_VFPv2,ISA_FP_DBL,
-      isa_nobit
+      "arm1022e",
+      cpu_opttab_arm1022e,
+      {
+        ISA_ARMv5te,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
     },
-    cpu_opttab_arm1022e,
-    &arm_fastmul_tune
+    TARGET_ARCH_armv5te
   },
   {
-    "xscale",
-    TARGET_CPU_xscale,
-    (TF_LDSCHED | TF_XSCALE),
-    "5TE", BASE_ARCH_5TE,
     {
-      ISA_ARMv5te,
-      isa_bit_xscale,
-      isa_nobit
+      "xscale",
+      NULL,
+      {
+        ISA_ARMv5te,
+        isa_bit_xscale,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_xscale_tune
+    TARGET_ARCH_armv5te
   },
   {
-    "iwmmxt",
-    TARGET_CPU_iwmmxt,
-    (TF_LDSCHED | TF_XSCALE),
-    "5TE", BASE_ARCH_5TE,
     {
-      ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,
-      isa_nobit
+      "iwmmxt",
+      NULL,
+      {
+        ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_xscale_tune
+    TARGET_ARCH_iwmmxt
   },
   {
-    "iwmmxt2",
-    TARGET_CPU_iwmmxt2,
-    (TF_LDSCHED | TF_XSCALE),
-    "5TE", BASE_ARCH_5TE,
     {
-      ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2,
-      isa_nobit
+      "iwmmxt2",
+      NULL,
+      {
+        ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_xscale_tune
+    TARGET_ARCH_iwmmxt2
   },
   {
-    "fa606te",
-    TARGET_CPU_fa606te,
-    (TF_LDSCHED),
-    "5TE", BASE_ARCH_5TE,
     {
-      ISA_ARMv5te,
-      isa_nobit
+      "fa606te",
+      NULL,
+      {
+        ISA_ARMv5te,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_9e_tune
+    TARGET_ARCH_armv5te
   },
   {
-    "fa626te",
-    TARGET_CPU_fa626te,
-    (TF_LDSCHED),
-    "5TE", BASE_ARCH_5TE,
     {
-      ISA_ARMv5te,
-      isa_nobit
+      "fa626te",
+      NULL,
+      {
+        ISA_ARMv5te,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_9e_tune
+    TARGET_ARCH_armv5te
   },
   {
-    "fmp626",
-    TARGET_CPU_fmp626,
-    (TF_LDSCHED),
-    "5TE", BASE_ARCH_5TE,
     {
-      ISA_ARMv5te,
-      isa_nobit
+      "fmp626",
+      NULL,
+      {
+        ISA_ARMv5te,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_9e_tune
+    TARGET_ARCH_armv5te
   },
   {
-    "fa726te",
-    TARGET_CPU_fa726te,
-    (TF_LDSCHED),
-    "5TE", BASE_ARCH_5TE,
     {
-      ISA_ARMv5te,
-      isa_nobit
+      "fa726te",
+      NULL,
+      {
+        ISA_ARMv5te,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_fa726te_tune
+    TARGET_ARCH_armv5te
   },
   {
-    "arm926ej-s",
-    TARGET_CPU_arm926ejs,
-    (TF_LDSCHED),
-    "5TEJ", BASE_ARCH_5TEJ,
     {
-      ISA_ARMv5tej,
-      ISA_VFPv2,ISA_FP_DBL,
-      isa_nobit
+      "arm926ej-s",
+      cpu_opttab_arm926ejs,
+      {
+        ISA_ARMv5tej,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
     },
-    cpu_opttab_arm926ejs,
-    &arm_9e_tune
+    TARGET_ARCH_armv5tej
   },
   {
-    "arm1026ej-s",
-    TARGET_CPU_arm1026ejs,
-    (TF_LDSCHED),
-    "5TEJ", BASE_ARCH_5TEJ,
     {
-      ISA_ARMv5tej,
-      ISA_VFPv2,ISA_FP_DBL,
-      isa_nobit
+      "arm1026ej-s",
+      cpu_opttab_arm1026ejs,
+      {
+        ISA_ARMv5tej,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
     },
-    cpu_opttab_arm1026ejs,
-    &arm_9e_tune
+    TARGET_ARCH_armv5tej
   },
   {
-    "arm1136j-s",
-    TARGET_CPU_arm1136js,
-    (TF_LDSCHED),
-    "6J", BASE_ARCH_6J,
     {
-      ISA_ARMv6j,
-      isa_nobit
+      "arm1136j-s",
+      NULL,
+      {
+        ISA_ARMv6j,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_9e_tune
+    TARGET_ARCH_armv6j
   },
   {
-    "arm1136jf-s",
-    TARGET_CPU_arm1136jfs,
-    (TF_LDSCHED),
-    "6J", BASE_ARCH_6J,
     {
-      ISA_ARMv6j,
-      ISA_VFPv2,ISA_FP_DBL,
-      isa_nobit
+      "arm1136jf-s",
+      NULL,
+      {
+        ISA_ARMv6j,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_9e_tune
+    TARGET_ARCH_armv6j
   },
   {
-    "arm1176jz-s",
-    TARGET_CPU_arm1176jzs,
-    (TF_LDSCHED),
-    "6KZ", BASE_ARCH_6KZ,
     {
-      ISA_ARMv6kz,
-      isa_nobit
+      "arm1176jz-s",
+      NULL,
+      {
+        ISA_ARMv6kz,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_9e_tune
+    TARGET_ARCH_armv6kz
   },
   {
-    "arm1176jzf-s",
-    TARGET_CPU_arm1176jzfs,
-    (TF_LDSCHED),
-    "6KZ", BASE_ARCH_6KZ,
     {
-      ISA_ARMv6kz,
-      ISA_VFPv2,ISA_FP_DBL,
-      isa_nobit
+      "arm1176jzf-s",
+      NULL,
+      {
+        ISA_ARMv6kz,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_9e_tune
+    TARGET_ARCH_armv6kz
   },
   {
-    "mpcorenovfp",
-    TARGET_CPU_mpcorenovfp,
-    (TF_LDSCHED),
-    "6K", BASE_ARCH_6K,
     {
-      ISA_ARMv6k,
-      isa_nobit
+      "mpcorenovfp",
+      NULL,
+      {
+        ISA_ARMv6k,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_9e_tune
+    TARGET_ARCH_armv6k
   },
   {
-    "mpcore",
-    TARGET_CPU_mpcore,
-    (TF_LDSCHED),
-    "6K", BASE_ARCH_6K,
     {
-      ISA_ARMv6k,
-      ISA_VFPv2,ISA_FP_DBL,
-      isa_nobit
+      "mpcore",
+      NULL,
+      {
+        ISA_ARMv6k,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_9e_tune
+    TARGET_ARCH_armv6k
   },
   {
-    "arm1156t2-s",
-    TARGET_CPU_arm1156t2s,
-    (TF_LDSCHED),
-    "6T2", BASE_ARCH_6T2,
     {
-      ISA_ARMv6t2,
-      isa_nobit
+      "arm1156t2-s",
+      NULL,
+      {
+        ISA_ARMv6t2,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_v6t2_tune
+    TARGET_ARCH_armv6t2
   },
   {
-    "arm1156t2f-s",
-    TARGET_CPU_arm1156t2fs,
-    (TF_LDSCHED),
-    "6T2", BASE_ARCH_6T2,
     {
-      ISA_ARMv6t2,
-      ISA_VFPv2,ISA_FP_DBL,
-      isa_nobit
+      "arm1156t2f-s",
+      NULL,
+      {
+        ISA_ARMv6t2,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_v6t2_tune
+    TARGET_ARCH_armv6t2
   },
   {
-    "cortex-m1",
-    TARGET_CPU_cortexm1,
-    (TF_LDSCHED),
-    "6M", BASE_ARCH_6M,
     {
-      ISA_ARMv6m,
-      isa_nobit
+      "cortex-m1",
+      NULL,
+      {
+        ISA_ARMv6m,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_v6m_tune
+    TARGET_ARCH_armv6_m
   },
   {
-    "cortex-m0",
-    TARGET_CPU_cortexm0,
-    (TF_LDSCHED),
-    "6M", BASE_ARCH_6M,
     {
-      ISA_ARMv6m,
-      isa_nobit
+      "cortex-m0",
+      NULL,
+      {
+        ISA_ARMv6m,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_v6m_tune
+    TARGET_ARCH_armv6_m
   },
   {
-    "cortex-m0plus",
-    TARGET_CPU_cortexm0plus,
-    (TF_LDSCHED),
-    "6M", BASE_ARCH_6M,
     {
-      ISA_ARMv6m,
-      isa_nobit
+      "cortex-m0plus",
+      NULL,
+      {
+        ISA_ARMv6m,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_v6m_tune
+    TARGET_ARCH_armv6_m
   },
   {
-    "cortex-m1.small-multiply",
-    TARGET_CPU_cortexm1,
-    (TF_LDSCHED | TF_SMALLMUL),
-    "6M", BASE_ARCH_6M,
     {
-      ISA_ARMv6m,
-      isa_nobit
+      "cortex-m1.small-multiply",
+      NULL,
+      {
+        ISA_ARMv6m,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_v6m_tune
+    TARGET_ARCH_armv6_m
   },
   {
-    "cortex-m0.small-multiply",
-    TARGET_CPU_cortexm0,
-    (TF_LDSCHED | TF_SMALLMUL),
-    "6M", BASE_ARCH_6M,
     {
-      ISA_ARMv6m,
-      isa_nobit
+      "cortex-m0.small-multiply",
+      NULL,
+      {
+        ISA_ARMv6m,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_v6m_tune
+    TARGET_ARCH_armv6_m
   },
   {
-    "cortex-m0plus.small-multiply",
-    TARGET_CPU_cortexm0plus,
-    (TF_LDSCHED | TF_SMALLMUL),
-    "6M", BASE_ARCH_6M,
     {
-      ISA_ARMv6m,
-      isa_nobit
+      "cortex-m0plus.small-multiply",
+      NULL,
+      {
+        ISA_ARMv6m,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_v6m_tune
+    TARGET_ARCH_armv6_m
   },
   {
-    "generic-armv7-a",
-    TARGET_CPU_genericv7a,
-    (TF_LDSCHED),
-    "7A", BASE_ARCH_7A,
     {
-      ISA_ARMv7a,
-      ISA_VFPv3,ISA_FP_DBL,
-      isa_nobit
+      "generic-armv7-a",
+      cpu_opttab_genericv7a,
+      {
+        ISA_ARMv7a,
+        ISA_VFPv3,ISA_FP_DBL,
+        isa_nobit
+      }
     },
-    cpu_opttab_genericv7a,
-    &arm_cortex_tune
+    TARGET_ARCH_armv7_a
   },
   {
-    "cortex-a5",
-    TARGET_CPU_cortexa5,
-    (TF_LDSCHED),
-    "7A", BASE_ARCH_7A,
     {
-      ISA_ARMv7a,
-      ISA_VFPv3,ISA_NEON,isa_bit_fp16conv,
-      isa_nobit
+      "cortex-a5",
+      cpu_opttab_cortexa5,
+      {
+        ISA_ARMv7a,
+        ISA_VFPv3,ISA_NEON,isa_bit_fp16conv,
+        isa_nobit
+      }
     },
-    cpu_opttab_cortexa5,
-    &arm_cortex_a5_tune
+    TARGET_ARCH_armv7_a
   },
   {
-    "cortex-a7",
-    TARGET_CPU_cortexa7,
-    (TF_LDSCHED),
-    "7A", BASE_ARCH_7A,
     {
-      ISA_ARMv7ve,
-      ISA_VFPv4,ISA_NEON,
-      isa_nobit
+      "cortex-a7",
+      cpu_opttab_cortexa7,
+      {
+        ISA_ARMv7ve,
+        ISA_VFPv4,ISA_NEON,
+        isa_nobit
+      }
     },
-    cpu_opttab_cortexa7,
-    &arm_cortex_a7_tune
+    TARGET_ARCH_armv7ve
   },
   {
-    "cortex-a8",
-    TARGET_CPU_cortexa8,
-    (TF_LDSCHED),
-    "7A", BASE_ARCH_7A,
     {
-      ISA_ARMv7a,
-      ISA_VFPv3,ISA_NEON,
-      isa_nobit
+      "cortex-a8",
+      cpu_opttab_cortexa8,
+      {
+        ISA_ARMv7a,
+        ISA_VFPv3,ISA_NEON,
+        isa_nobit
+      }
     },
-    cpu_opttab_cortexa8,
-    &arm_cortex_a8_tune
+    TARGET_ARCH_armv7_a
   },
   {
-    "cortex-a9",
-    TARGET_CPU_cortexa9,
-    (TF_LDSCHED),
-    "7A", BASE_ARCH_7A,
     {
-      ISA_ARMv7a,
-      ISA_VFPv3,ISA_NEON,isa_bit_fp16conv,
-      isa_nobit
+      "cortex-a9",
+      cpu_opttab_cortexa9,
+      {
+        ISA_ARMv7a,
+        ISA_VFPv3,ISA_NEON,isa_bit_fp16conv,
+        isa_nobit
+      }
     },
-    cpu_opttab_cortexa9,
-    &arm_cortex_a9_tune
+    TARGET_ARCH_armv7_a
   },
   {
-    "cortex-a12",
-    TARGET_CPU_cortexa17,
-    (TF_LDSCHED),
-    "7A", BASE_ARCH_7A,
     {
-      ISA_ARMv7ve,
-      ISA_VFPv4,ISA_NEON,
-      isa_nobit
+      "cortex-a12",
+      cpu_opttab_cortexa12,
+      {
+        ISA_ARMv7ve,
+        ISA_VFPv4,ISA_NEON,
+        isa_nobit
+      }
     },
-    cpu_opttab_cortexa12,
-    &arm_cortex_a12_tune
+    TARGET_ARCH_armv7ve
   },
   {
-    "cortex-a15",
-    TARGET_CPU_cortexa15,
-    (TF_LDSCHED),
-    "7A", BASE_ARCH_7A,
     {
-      ISA_ARMv7ve,
-      ISA_VFPv4,ISA_NEON,
-      isa_nobit
+      "cortex-a15",
+      cpu_opttab_cortexa15,
+      {
+        ISA_ARMv7ve,
+        ISA_VFPv4,ISA_NEON,
+        isa_nobit
+      }
     },
-    cpu_opttab_cortexa15,
-    &arm_cortex_a15_tune
+    TARGET_ARCH_armv7ve
   },
   {
-    "cortex-a17",
-    TARGET_CPU_cortexa17,
-    (TF_LDSCHED),
-    "7A", BASE_ARCH_7A,
     {
-      ISA_ARMv7ve,
-      ISA_VFPv4,ISA_NEON,
-      isa_nobit
+      "cortex-a17",
+      cpu_opttab_cortexa17,
+      {
+        ISA_ARMv7ve,
+        ISA_VFPv4,ISA_NEON,
+        isa_nobit
+      }
     },
-    cpu_opttab_cortexa17,
-    &arm_cortex_a12_tune
+    TARGET_ARCH_armv7ve
   },
   {
-    "cortex-r4",
-    TARGET_CPU_cortexr4,
-    (TF_LDSCHED),
-    "7R", BASE_ARCH_7R,
     {
-      ISA_ARMv7r,
-      isa_nobit
+      "cortex-r4",
+      NULL,
+      {
+        ISA_ARMv7r,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_cortex_tune
+    TARGET_ARCH_armv7_r
   },
   {
-    "cortex-r4f",
-    TARGET_CPU_cortexr4f,
-    (TF_LDSCHED),
-    "7R", BASE_ARCH_7R,
     {
-      ISA_ARMv7r,
-      ISA_VFPv3,ISA_FP_DBL,
-      isa_nobit
+      "cortex-r4f",
+      NULL,
+      {
+        ISA_ARMv7r,
+        ISA_VFPv3,ISA_FP_DBL,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_cortex_tune
+    TARGET_ARCH_armv7_r
   },
   {
-    "cortex-r5",
-    TARGET_CPU_cortexr5,
-    (TF_LDSCHED),
-    "7R", BASE_ARCH_7R,
     {
-      ISA_ARMv7r,
-      isa_bit_adiv,
-      ISA_VFPv3,ISA_FP_DBL,
-      isa_nobit
+      "cortex-r5",
+      cpu_opttab_cortexr5,
+      {
+        ISA_ARMv7r,
+        isa_bit_adiv,
+        ISA_VFPv3,ISA_FP_DBL,
+        isa_nobit
+      }
     },
-    cpu_opttab_cortexr5,
-    &arm_cortex_tune
+    TARGET_ARCH_armv7_r
   },
   {
-    "cortex-r7",
-    TARGET_CPU_cortexr7,
-    (TF_LDSCHED),
-    "7R", BASE_ARCH_7R,
     {
-      ISA_ARMv7r,
-      isa_bit_adiv,
-      ISA_VFPv3,ISA_FP_DBL,
-      isa_nobit
+      "cortex-r7",
+      cpu_opttab_cortexr7,
+      {
+        ISA_ARMv7r,
+        isa_bit_adiv,
+        ISA_VFPv3,ISA_FP_DBL,
+        isa_nobit
+      }
     },
-    cpu_opttab_cortexr7,
-    &arm_cortex_tune
+    TARGET_ARCH_armv7_r
   },
   {
-    "cortex-r8",
-    TARGET_CPU_cortexr7,
-    (TF_LDSCHED),
-    "7R", BASE_ARCH_7R,
     {
-      ISA_ARMv7r,
-      isa_bit_adiv,
-      ISA_VFPv3,ISA_FP_DBL,
-      isa_nobit
+      "cortex-r8",
+      cpu_opttab_cortexr8,
+      {
+        ISA_ARMv7r,
+        isa_bit_adiv,
+        ISA_VFPv3,ISA_FP_DBL,
+        isa_nobit
+      }
     },
-    cpu_opttab_cortexr8,
-    &arm_cortex_tune
+    TARGET_ARCH_armv7_r
   },
   {
-    "cortex-m7",
-    TARGET_CPU_cortexm7,
-    (TF_LDSCHED),
-    "7EM", BASE_ARCH_7EM,
     {
-      ISA_ARMv7em,
-      ISA_FPv5,ISA_FP_DBL,
-      isa_quirk_no_volatile_ce,
-      isa_nobit
+      "cortex-m7",
+      cpu_opttab_cortexm7,
+      {
+        ISA_ARMv7em,
+        ISA_FPv5,ISA_FP_DBL,
+        isa_quirk_no_volatile_ce,
+        isa_nobit
+      }
     },
-    cpu_opttab_cortexm7,
-    &arm_cortex_m7_tune
+    TARGET_ARCH_armv7e_m
   },
   {
-    "cortex-m4",
-    TARGET_CPU_cortexm4,
-    (TF_LDSCHED),
-    "7EM", BASE_ARCH_7EM,
     {
-      ISA_ARMv7em,
-      ISA_VFPv4,
-      isa_nobit
+      "cortex-m4",
+      cpu_opttab_cortexm4,
+      {
+        ISA_ARMv7em,
+        ISA_VFPv4,
+        isa_nobit
+      }
     },
-    cpu_opttab_cortexm4,
-    &arm_v7m_tune
+    TARGET_ARCH_armv7e_m
   },
   {
-    "cortex-m3",
-    TARGET_CPU_cortexm3,
-    (TF_LDSCHED),
-    "7M", BASE_ARCH_7M,
     {
-      ISA_ARMv7m,
-      isa_quirk_cm3_ldrd,
-      isa_nobit
+      "cortex-m3",
+      NULL,
+      {
+        ISA_ARMv7m,
+        isa_quirk_cm3_ldrd,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_v7m_tune
+    TARGET_ARCH_armv7_m
   },
   {
-    "marvell-pj4",
-    TARGET_CPU_marvell_pj4,
-    (TF_LDSCHED),
-    "7A", BASE_ARCH_7A,
     {
-      ISA_ARMv7a,
-      isa_nobit
+      "marvell-pj4",
+      NULL,
+      {
+        ISA_ARMv7a,
+        isa_nobit
+      }
     },
-    NULL,
-    &arm_marvell_pj4_tune
+    TARGET_ARCH_armv7_a
   },
   {
-    "cortex-a15.cortex-a7",
-    TARGET_CPU_cortexa7,
-    (TF_LDSCHED),
-    "7A", BASE_ARCH_7A,
     {
-      ISA_ARMv7ve,
-      ISA_VFPv4,ISA_NEON,
-      isa_nobit
+      "cortex-a15.cortex-a7",
+      cpu_opttab_cortexa15cortexa7,
+      {
+        ISA_ARMv7ve,
+        ISA_VFPv4,ISA_NEON,
+        isa_nobit
+      }
     },
-    cpu_opttab_cortexa15cortexa7,
-    &arm_cortex_a15_tune
+    TARGET_ARCH_armv7ve
   },
   {
-    "cortex-a17.cortex-a7",
-    TARGET_CPU_cortexa7,
-    (TF_LDSCHED),
-    "7A", BASE_ARCH_7A,
     {
-      ISA_ARMv7ve,
-      ISA_VFPv4,ISA_NEON,
-      isa_nobit
+      "cortex-a17.cortex-a7",
+      cpu_opttab_cortexa17cortexa7,
+      {
+        ISA_ARMv7ve,
+        ISA_VFPv4,ISA_NEON,
+        isa_nobit
+      }
     },
-    cpu_opttab_cortexa17cortexa7,
-    &arm_cortex_a12_tune
+    TARGET_ARCH_armv7ve
   },
   {
-    "cortex-a32",
-    TARGET_CPU_cortexa53,
-    (TF_LDSCHED),
-    "8A", BASE_ARCH_8A,
     {
-      ISA_ARMv8a,
-      isa_bit_crc32,
-      ISA_FP_ARMv8,ISA_NEON,
-      isa_nobit
+      "cortex-a32",
+      cpu_opttab_cortexa32,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
     },
-    cpu_opttab_cortexa32,
-    &arm_cortex_a35_tune
+    TARGET_ARCH_armv8_a
   },
   {
-    "cortex-a35",
-    TARGET_CPU_cortexa53,
-    (TF_LDSCHED),
-    "8A", BASE_ARCH_8A,
     {
-      ISA_ARMv8a,
-      isa_bit_crc32,
-      ISA_FP_ARMv8,ISA_NEON,
-      isa_nobit
+      "cortex-a35",
+      cpu_opttab_cortexa35,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
     },
-    cpu_opttab_cortexa35,
-    &arm_cortex_a35_tune
+    TARGET_ARCH_armv8_a
   },
   {
-    "cortex-a53",
-    TARGET_CPU_cortexa53,
-    (TF_LDSCHED),
-    "8A", BASE_ARCH_8A,
     {
-      ISA_ARMv8a,
-      isa_bit_crc32,
-      ISA_FP_ARMv8,ISA_NEON,
-      isa_nobit
+      "cortex-a53",
+      cpu_opttab_cortexa53,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
     },
-    cpu_opttab_cortexa53,
-    &arm_cortex_a53_tune
+    TARGET_ARCH_armv8_a
   },
   {
-    "cortex-a57",
-    TARGET_CPU_cortexa57,
-    (TF_LDSCHED),
-    "8A", BASE_ARCH_8A,
     {
-      ISA_ARMv8a,
-      isa_bit_crc32,
-      ISA_FP_ARMv8,ISA_NEON,
-      isa_nobit
+      "cortex-a57",
+      cpu_opttab_cortexa57,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
     },
-    cpu_opttab_cortexa57,
-    &arm_cortex_a57_tune
+    TARGET_ARCH_armv8_a
   },
   {
-    "cortex-a72",
-    TARGET_CPU_cortexa57,
-    (TF_LDSCHED),
-    "8A", BASE_ARCH_8A,
     {
-      ISA_ARMv8a,
-      isa_bit_crc32,
-      ISA_FP_ARMv8,ISA_NEON,
-      isa_nobit
+      "cortex-a72",
+      cpu_opttab_cortexa72,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
     },
-    cpu_opttab_cortexa72,
-    &arm_cortex_a57_tune
+    TARGET_ARCH_armv8_a
   },
   {
-    "cortex-a73",
-    TARGET_CPU_cortexa57,
-    (TF_LDSCHED),
-    "8A", BASE_ARCH_8A,
     {
-      ISA_ARMv8a,
-      isa_bit_crc32,
-      ISA_FP_ARMv8,ISA_NEON,
-      isa_nobit
+      "cortex-a73",
+      cpu_opttab_cortexa73,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
     },
-    cpu_opttab_cortexa73,
-    &arm_cortex_a73_tune
+    TARGET_ARCH_armv8_a
   },
   {
-    "exynos-m1",
-    TARGET_CPU_exynosm1,
-    (TF_LDSCHED),
-    "8A", BASE_ARCH_8A,
     {
-      ISA_ARMv8a,
-      isa_bit_crc32,
-      ISA_FP_ARMv8,ISA_NEON,
-      isa_nobit
+      "exynos-m1",
+      cpu_opttab_exynosm1,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
     },
-    cpu_opttab_exynosm1,
-    &arm_exynosm1_tune
+    TARGET_ARCH_armv8_a
   },
   {
-    "falkor",
-    TARGET_CPU_cortexa57,
-    (TF_LDSCHED),
-    "8A", BASE_ARCH_8A,
     {
-      ISA_ARMv8a,
-      isa_bit_crc32,
-      ISA_FP_ARMv8,ISA_NEON,
-      isa_nobit
+      "falkor",
+      cpu_opttab_falkor,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "qdf24xx",
+      cpu_opttab_qdf24xx,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "xgene1",
+      cpu_opttab_xgene1,
+      {
+        ISA_ARMv8a,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a57.cortex-a53",
+      cpu_opttab_cortexa57cortexa53,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a72.cortex-a53",
+      cpu_opttab_cortexa72cortexa53,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
     },
-    cpu_opttab_falkor,
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a73.cortex-a35",
+      cpu_opttab_cortexa73cortexa35,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a73.cortex-a53",
+      cpu_opttab_cortexa73cortexa53,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-m23",
+      NULL,
+      {
+        ISA_ARMv8m_base,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_m_base
+  },
+  {
+    {
+      "cortex-m33",
+      cpu_opttab_cortexm33,
+      {
+        ISA_ARMv8m_main,
+        isa_bit_ARMv7em,
+        ISA_FPv5,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_m_main
+  },
+  {{NULL, NULL, {isa_nobit}}, TARGET_ARCH_arm_none}
+};
+static const cpu_tune all_tunes[] =
+{
+  { /* arm2.  */
+    TARGET_CPU_arm2,
+    (TF_CO_PROC | TF_NO_MODE32),
+    &arm_slowmul_tune
+  },
+  { /* arm250.  */
+    TARGET_CPU_arm250,
+    (TF_CO_PROC | TF_NO_MODE32),
+    &arm_slowmul_tune
+  },
+  { /* arm3.  */
+    TARGET_CPU_arm3,
+    (TF_CO_PROC | TF_NO_MODE32),
+    &arm_slowmul_tune
+  },
+  { /* arm6.  */
+    TARGET_CPU_arm6,
+    (TF_CO_PROC),
+    &arm_slowmul_tune
+  },
+  { /* arm60.  */
+    TARGET_CPU_arm60,
+    (TF_CO_PROC),
+    &arm_slowmul_tune
+  },
+  { /* arm600.  */
+    TARGET_CPU_arm600,
+    (TF_CO_PROC | TF_WBUF),
+    &arm_slowmul_tune
+  },
+  { /* arm610.  */
+    TARGET_CPU_arm610,
+    (TF_WBUF),
+    &arm_slowmul_tune
+  },
+  { /* arm620.  */
+    TARGET_CPU_arm620,
+    (TF_CO_PROC | TF_WBUF),
+    &arm_slowmul_tune
+  },
+  { /* arm7.  */
+    TARGET_CPU_arm7,
+    (TF_CO_PROC),
+    &arm_slowmul_tune
+  },
+  { /* arm7d.  */
+    TARGET_CPU_arm7d,
+    (TF_CO_PROC),
+    &arm_slowmul_tune
+  },
+  { /* arm7di.  */
+    TARGET_CPU_arm7di,
+    (TF_CO_PROC),
+    &arm_slowmul_tune
+  },
+  { /* arm70.  */
+    TARGET_CPU_arm70,
+    (TF_CO_PROC),
+    &arm_slowmul_tune
+  },
+  { /* arm700.  */
+    TARGET_CPU_arm700,
+    (TF_CO_PROC | TF_WBUF),
+    &arm_slowmul_tune
+  },
+  { /* arm700i.  */
+    TARGET_CPU_arm700i,
+    (TF_CO_PROC | TF_WBUF),
+    &arm_slowmul_tune
+  },
+  { /* arm710.  */
+    TARGET_CPU_arm710,
+    (TF_WBUF),
+    &arm_slowmul_tune
+  },
+  { /* arm720.  */
+    TARGET_CPU_arm720,
+    (TF_WBUF),
+    &arm_slowmul_tune
+  },
+  { /* arm710c.  */
+    TARGET_CPU_arm710c,
+    (TF_WBUF),
+    &arm_slowmul_tune
+  },
+  { /* arm7100.  */
+    TARGET_CPU_arm7100,
+    (TF_WBUF),
+    &arm_slowmul_tune
+  },
+  { /* arm7500.  */
+    TARGET_CPU_arm7500,
+    (TF_WBUF),
+    &arm_slowmul_tune
+  },
+  { /* arm7500fe.  */
+    TARGET_CPU_arm7500fe,
+    (TF_CO_PROC | TF_WBUF),
+    &arm_slowmul_tune
+  },
+  { /* arm7m.  */
+    TARGET_CPU_arm7m,
+    (TF_CO_PROC),
+    &arm_fastmul_tune
+  },
+  { /* arm7dm.  */
+    TARGET_CPU_arm7dm,
+    (TF_CO_PROC),
+    &arm_fastmul_tune
+  },
+  { /* arm7dmi.  */
+    TARGET_CPU_arm7dmi,
+    (TF_CO_PROC),
+    &arm_fastmul_tune
+  },
+  { /* arm8.  */
+    TARGET_CPU_arm8,
+    (TF_LDSCHED),
+    &arm_fastmul_tune
+  },
+  { /* arm810.  */
+    TARGET_CPU_arm810,
+    (TF_LDSCHED),
+    &arm_fastmul_tune
+  },
+  { /* strongarm.  */
+    TARGET_CPU_strongarm,
+    (TF_LDSCHED | TF_STRONG),
+    &arm_strongarm_tune
+  },
+  { /* strongarm110.  */
+    TARGET_CPU_strongarm110,
+    (TF_LDSCHED | TF_STRONG),
+    &arm_strongarm_tune
+  },
+  { /* strongarm1100.  */
+    TARGET_CPU_strongarm1100,
+    (TF_LDSCHED | TF_STRONG),
+    &arm_strongarm_tune
+  },
+  { /* strongarm1110.  */
+    TARGET_CPU_strongarm1110,
+    (TF_LDSCHED | TF_STRONG),
+    &arm_strongarm_tune
+  },
+  { /* fa526.  */
+    TARGET_CPU_fa526,
+    (TF_LDSCHED),
+    &arm_fastmul_tune
+  },
+  { /* fa626.  */
+    TARGET_CPU_fa626,
+    (TF_LDSCHED),
+    &arm_fastmul_tune
+  },
+  { /* arm7tdmi.  */
+    TARGET_CPU_arm7tdmi,
+    (TF_CO_PROC),
+    &arm_fastmul_tune
+  },
+  { /* arm7tdmi-s.  */
+    TARGET_CPU_arm7tdmis,
+    (TF_CO_PROC),
+    &arm_fastmul_tune
+  },
+  { /* arm710t.  */
+    TARGET_CPU_arm710t,
+    (TF_WBUF),
+    &arm_fastmul_tune
+  },
+  { /* arm720t.  */
+    TARGET_CPU_arm720t,
+    (TF_WBUF),
+    &arm_fastmul_tune
+  },
+  { /* arm740t.  */
+    TARGET_CPU_arm740t,
+    (TF_WBUF),
+    &arm_fastmul_tune
+  },
+  { /* arm9.  */
+    TARGET_CPU_arm9,
+    (TF_LDSCHED),
+    &arm_fastmul_tune
+  },
+  { /* arm9tdmi.  */
+    TARGET_CPU_arm9tdmi,
+    (TF_LDSCHED),
+    &arm_fastmul_tune
+  },
+  { /* arm920.  */
+    TARGET_CPU_arm920,
+    (TF_LDSCHED),
+    &arm_fastmul_tune
+  },
+  { /* arm920t.  */
+    TARGET_CPU_arm920t,
+    (TF_LDSCHED),
+    &arm_fastmul_tune
+  },
+  { /* arm922t.  */
+    TARGET_CPU_arm922t,
+    (TF_LDSCHED),
+    &arm_fastmul_tune
+  },
+  { /* arm940t.  */
+    TARGET_CPU_arm940t,
+    (TF_LDSCHED),
+    &arm_fastmul_tune
+  },
+  { /* ep9312.  */
+    TARGET_CPU_ep9312,
+    (TF_LDSCHED),
+    &arm_fastmul_tune
+  },
+  { /* arm10tdmi.  */
+    TARGET_CPU_arm10tdmi,
+    (TF_LDSCHED),
+    &arm_fastmul_tune
+  },
+  { /* arm1020t.  */
+    TARGET_CPU_arm1020t,
+    (TF_LDSCHED),
+    &arm_fastmul_tune
+  },
+  { /* arm9e.  */
+    TARGET_CPU_arm9e,
+    (TF_LDSCHED),
+    &arm_9e_tune
+  },
+  { /* arm946e-s.  */
+    TARGET_CPU_arm946es,
+    (TF_LDSCHED),
+    &arm_9e_tune
+  },
+  { /* arm966e-s.  */
+    TARGET_CPU_arm966es,
+    (TF_LDSCHED),
+    &arm_9e_tune
+  },
+  { /* arm968e-s.  */
+    TARGET_CPU_arm968es,
+    (TF_LDSCHED),
+    &arm_9e_tune
+  },
+  { /* arm10e.  */
+    TARGET_CPU_arm10e,
+    (TF_LDSCHED),
+    &arm_fastmul_tune
+  },
+  { /* arm1020e.  */
+    TARGET_CPU_arm1020e,
+    (TF_LDSCHED),
+    &arm_fastmul_tune
+  },
+  { /* arm1022e.  */
+    TARGET_CPU_arm1022e,
+    (TF_LDSCHED),
+    &arm_fastmul_tune
+  },
+  { /* xscale.  */
+    TARGET_CPU_xscale,
+    (TF_LDSCHED | TF_XSCALE),
+    &arm_xscale_tune
+  },
+  { /* iwmmxt.  */
+    TARGET_CPU_iwmmxt,
+    (TF_LDSCHED | TF_XSCALE),
+    &arm_xscale_tune
+  },
+  { /* iwmmxt2.  */
+    TARGET_CPU_iwmmxt2,
+    (TF_LDSCHED | TF_XSCALE),
+    &arm_xscale_tune
+  },
+  { /* fa606te.  */
+    TARGET_CPU_fa606te,
+    (TF_LDSCHED),
+    &arm_9e_tune
+  },
+  { /* fa626te.  */
+    TARGET_CPU_fa626te,
+    (TF_LDSCHED),
+    &arm_9e_tune
+  },
+  { /* fmp626.  */
+    TARGET_CPU_fmp626,
+    (TF_LDSCHED),
+    &arm_9e_tune
+  },
+  { /* fa726te.  */
+    TARGET_CPU_fa726te,
+    (TF_LDSCHED),
+    &arm_fa726te_tune
+  },
+  { /* arm926ej-s.  */
+    TARGET_CPU_arm926ejs,
+    (TF_LDSCHED),
+    &arm_9e_tune
+  },
+  { /* arm1026ej-s.  */
+    TARGET_CPU_arm1026ejs,
+    (TF_LDSCHED),
+    &arm_9e_tune
+  },
+  { /* arm1136j-s.  */
+    TARGET_CPU_arm1136js,
+    (TF_LDSCHED),
+    &arm_9e_tune
+  },
+  { /* arm1136jf-s.  */
+    TARGET_CPU_arm1136jfs,
+    (TF_LDSCHED),
+    &arm_9e_tune
+  },
+  { /* arm1176jz-s.  */
+    TARGET_CPU_arm1176jzs,
+    (TF_LDSCHED),
+    &arm_9e_tune
+  },
+  { /* arm1176jzf-s.  */
+    TARGET_CPU_arm1176jzfs,
+    (TF_LDSCHED),
+    &arm_9e_tune
+  },
+  { /* mpcorenovfp.  */
+    TARGET_CPU_mpcorenovfp,
+    (TF_LDSCHED),
+    &arm_9e_tune
+  },
+  { /* mpcore.  */
+    TARGET_CPU_mpcore,
+    (TF_LDSCHED),
+    &arm_9e_tune
+  },
+  { /* arm1156t2-s.  */
+    TARGET_CPU_arm1156t2s,
+    (TF_LDSCHED),
+    &arm_v6t2_tune
+  },
+  { /* arm1156t2f-s.  */
+    TARGET_CPU_arm1156t2fs,
+    (TF_LDSCHED),
+    &arm_v6t2_tune
+  },
+  { /* cortex-m1.  */
+    TARGET_CPU_cortexm1,
+    (TF_LDSCHED),
+    &arm_v6m_tune
+  },
+  { /* cortex-m0.  */
+    TARGET_CPU_cortexm0,
+    (TF_LDSCHED),
+    &arm_v6m_tune
+  },
+  { /* cortex-m0plus.  */
+    TARGET_CPU_cortexm0plus,
+    (TF_LDSCHED),
+    &arm_v6m_tune
+  },
+  { /* cortex-m1.small-multiply.  */
+    TARGET_CPU_cortexm1,
+    (TF_LDSCHED | TF_SMALLMUL),
+    &arm_v6m_tune
+  },
+  { /* cortex-m0.small-multiply.  */
+    TARGET_CPU_cortexm0,
+    (TF_LDSCHED | TF_SMALLMUL),
+    &arm_v6m_tune
+  },
+  { /* cortex-m0plus.small-multiply.  */
+    TARGET_CPU_cortexm0plus,
+    (TF_LDSCHED | TF_SMALLMUL),
+    &arm_v6m_tune
+  },
+  { /* generic-armv7-a.  */
+    TARGET_CPU_genericv7a,
+    (TF_LDSCHED),
+    &arm_cortex_tune
+  },
+  { /* cortex-a5.  */
+    TARGET_CPU_cortexa5,
+    (TF_LDSCHED),
+    &arm_cortex_a5_tune
+  },
+  { /* cortex-a7.  */
+    TARGET_CPU_cortexa7,
+    (TF_LDSCHED),
+    &arm_cortex_a7_tune
+  },
+  { /* cortex-a8.  */
+    TARGET_CPU_cortexa8,
+    (TF_LDSCHED),
+    &arm_cortex_a8_tune
+  },
+  { /* cortex-a9.  */
+    TARGET_CPU_cortexa9,
+    (TF_LDSCHED),
+    &arm_cortex_a9_tune
+  },
+  { /* cortex-a12.  */
+    TARGET_CPU_cortexa17,
+    (TF_LDSCHED),
+    &arm_cortex_a12_tune
+  },
+  { /* cortex-a15.  */
+    TARGET_CPU_cortexa15,
+    (TF_LDSCHED),
+    &arm_cortex_a15_tune
+  },
+  { /* cortex-a17.  */
+    TARGET_CPU_cortexa17,
+    (TF_LDSCHED),
+    &arm_cortex_a12_tune
+  },
+  { /* cortex-r4.  */
+    TARGET_CPU_cortexr4,
+    (TF_LDSCHED),
+    &arm_cortex_tune
+  },
+  { /* cortex-r4f.  */
+    TARGET_CPU_cortexr4f,
+    (TF_LDSCHED),
+    &arm_cortex_tune
+  },
+  { /* cortex-r5.  */
+    TARGET_CPU_cortexr5,
+    (TF_LDSCHED),
+    &arm_cortex_tune
+  },
+  { /* cortex-r7.  */
+    TARGET_CPU_cortexr7,
+    (TF_LDSCHED),
+    &arm_cortex_tune
+  },
+  { /* cortex-r8.  */
+    TARGET_CPU_cortexr7,
+    (TF_LDSCHED),
+    &arm_cortex_tune
+  },
+  { /* cortex-m7.  */
+    TARGET_CPU_cortexm7,
+    (TF_LDSCHED),
+    &arm_cortex_m7_tune
+  },
+  { /* cortex-m4.  */
+    TARGET_CPU_cortexm4,
+    (TF_LDSCHED),
+    &arm_v7m_tune
+  },
+  { /* cortex-m3.  */
+    TARGET_CPU_cortexm3,
+    (TF_LDSCHED),
+    &arm_v7m_tune
+  },
+  { /* marvell-pj4.  */
+    TARGET_CPU_marvell_pj4,
+    (TF_LDSCHED),
+    &arm_marvell_pj4_tune
+  },
+  { /* cortex-a15.cortex-a7.  */
+    TARGET_CPU_cortexa7,
+    (TF_LDSCHED),
+    &arm_cortex_a15_tune
+  },
+  { /* cortex-a17.cortex-a7.  */
+    TARGET_CPU_cortexa7,
+    (TF_LDSCHED),
+    &arm_cortex_a12_tune
+  },
+  { /* cortex-a32.  */
+    TARGET_CPU_cortexa53,
+    (TF_LDSCHED),
+    &arm_cortex_a35_tune
+  },
+  { /* cortex-a35.  */
+    TARGET_CPU_cortexa53,
+    (TF_LDSCHED),
+    &arm_cortex_a35_tune
+  },
+  { /* cortex-a53.  */
+    TARGET_CPU_cortexa53,
+    (TF_LDSCHED),
+    &arm_cortex_a53_tune
+  },
+  { /* cortex-a57.  */
+    TARGET_CPU_cortexa57,
+    (TF_LDSCHED),
+    &arm_cortex_a57_tune
+  },
+  { /* cortex-a72.  */
+    TARGET_CPU_cortexa57,
+    (TF_LDSCHED),
+    &arm_cortex_a57_tune
+  },
+  { /* cortex-a73.  */
+    TARGET_CPU_cortexa57,
+    (TF_LDSCHED),
+    &arm_cortex_a73_tune
+  },
+  { /* exynos-m1.  */
+    TARGET_CPU_exynosm1,
+    (TF_LDSCHED),
+    &arm_exynosm1_tune
+  },
+  { /* falkor.  */
+    TARGET_CPU_cortexa57,
+    (TF_LDSCHED),
     &arm_qdf24xx_tune
   },
-  {
-    "qdf24xx",
+  { /* qdf24xx.  */
     TARGET_CPU_cortexa57,
     (TF_LDSCHED),
-    "8A", BASE_ARCH_8A,
-    {
-      ISA_ARMv8a,
-      isa_bit_crc32,
-      ISA_FP_ARMv8,ISA_NEON,
-      isa_nobit
-    },
-    cpu_opttab_qdf24xx,
     &arm_qdf24xx_tune
   },
-  {
-    "xgene1",
+  { /* xgene1.  */
     TARGET_CPU_xgene1,
     (TF_LDSCHED),
-    "8A", BASE_ARCH_8A,
-    {
-      ISA_ARMv8a,
-      ISA_FP_ARMv8,ISA_NEON,
-      isa_nobit
-    },
-    cpu_opttab_xgene1,
     &arm_xgene1_tune
   },
-  {
-    "cortex-a57.cortex-a53",
+  { /* cortex-a57.cortex-a53.  */
     TARGET_CPU_cortexa53,
     (TF_LDSCHED),
-    "8A", BASE_ARCH_8A,
-    {
-      ISA_ARMv8a,
-      isa_bit_crc32,
-      ISA_FP_ARMv8,ISA_NEON,
-      isa_nobit
-    },
-    cpu_opttab_cortexa57cortexa53,
     &arm_cortex_a57_tune
   },
-  {
-    "cortex-a72.cortex-a53",
+  { /* cortex-a72.cortex-a53.  */
     TARGET_CPU_cortexa53,
     (TF_LDSCHED),
-    "8A", BASE_ARCH_8A,
-    {
-      ISA_ARMv8a,
-      isa_bit_crc32,
-      ISA_FP_ARMv8,ISA_NEON,
-      isa_nobit
-    },
-    cpu_opttab_cortexa72cortexa53,
     &arm_cortex_a57_tune
   },
-  {
-    "cortex-a73.cortex-a35",
+  { /* cortex-a73.cortex-a35.  */
     TARGET_CPU_cortexa53,
     (TF_LDSCHED),
-    "8A", BASE_ARCH_8A,
-    {
-      ISA_ARMv8a,
-      isa_bit_crc32,
-      ISA_FP_ARMv8,ISA_NEON,
-      isa_nobit
-    },
-    cpu_opttab_cortexa73cortexa35,
     &arm_cortex_a73_tune
   },
-  {
-    "cortex-a73.cortex-a53",
+  { /* cortex-a73.cortex-a53.  */
     TARGET_CPU_cortexa53,
     (TF_LDSCHED),
-    "8A", BASE_ARCH_8A,
-    {
-      ISA_ARMv8a,
-      isa_bit_crc32,
-      ISA_FP_ARMv8,ISA_NEON,
-      isa_nobit
-    },
-    cpu_opttab_cortexa73cortexa53,
     &arm_cortex_a73_tune
   },
-  {
-    "cortex-m23",
+  { /* cortex-m23.  */
     TARGET_CPU_cortexm23,
     (TF_LDSCHED),
-    "8M_BASE", BASE_ARCH_8M_BASE,
-    {
-      ISA_ARMv8m_base,
-      isa_nobit
-    },
-    NULL,
     &arm_v6m_tune
   },
-  {
-    "cortex-m33",
+  { /* cortex-m33.  */
     TARGET_CPU_cortexm33,
     (TF_LDSCHED),
-    "8M_MAIN", BASE_ARCH_8M_MAIN,
-    {
-      ISA_ARMv8m_main,
-      isa_bit_ARMv7em,
-      ISA_FPv5,
-      isa_nobit
-    },
-    cpu_opttab_cortexm33,
     &arm_v7m_tune
   },
-  {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL, NULL}
+  {TARGET_CPU_arm_none, 0, NULL}
 };
-
-static const struct cpu_option arch_opttab_armv5e[] = {
+static const struct cpu_arch_extension arch_opttab_armv5e[] = {
   {
     "fp", false,
     { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
@@ -1817,7 +2260,7 @@ static const struct cpu_option arch_opttab_armv5e[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option arch_opttab_armv5te[] = {
+static const struct cpu_arch_extension arch_opttab_armv5te[] = {
   {
     "fp", false,
     { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
@@ -1833,7 +2276,7 @@ static const struct cpu_option arch_opttab_armv5te[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option arch_opttab_armv5tej[] = {
+static const struct cpu_arch_extension arch_opttab_armv5tej[] = {
   {
     "fp", false,
     { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
@@ -1849,7 +2292,7 @@ static const struct cpu_option arch_opttab_armv5tej[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option arch_opttab_armv6[] = {
+static const struct cpu_arch_extension arch_opttab_armv6[] = {
   {
     "fp", false,
     { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
@@ -1865,7 +2308,7 @@ static const struct cpu_option arch_opttab_armv6[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option arch_opttab_armv6j[] = {
+static const struct cpu_arch_extension arch_opttab_armv6j[] = {
   {
     "fp", false,
     { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
@@ -1881,7 +2324,7 @@ static const struct cpu_option arch_opttab_armv6j[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option arch_opttab_armv6k[] = {
+static const struct cpu_arch_extension arch_opttab_armv6k[] = {
   {
     "fp", false,
     { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
@@ -1897,7 +2340,7 @@ static const struct cpu_option arch_opttab_armv6k[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option arch_opttab_armv6z[] = {
+static const struct cpu_arch_extension arch_opttab_armv6z[] = {
   {
     "fp", false,
     { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
@@ -1913,7 +2356,7 @@ static const struct cpu_option arch_opttab_armv6z[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option arch_opttab_armv6kz[] = {
+static const struct cpu_arch_extension arch_opttab_armv6kz[] = {
   {
     "fp", false,
     { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
@@ -1929,7 +2372,7 @@ static const struct cpu_option arch_opttab_armv6kz[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option arch_opttab_armv6zk[] = {
+static const struct cpu_arch_extension arch_opttab_armv6zk[] = {
   {
     "fp", false,
     { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
@@ -1945,7 +2388,7 @@ static const struct cpu_option arch_opttab_armv6zk[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option arch_opttab_armv6t2[] = {
+static const struct cpu_arch_extension arch_opttab_armv6t2[] = {
   {
     "fp", false,
     { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
@@ -1961,7 +2404,7 @@ static const struct cpu_option arch_opttab_armv6t2[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option arch_opttab_armv7[] = {
+static const struct cpu_arch_extension arch_opttab_armv7[] = {
   {
     "fp", false,
     { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
@@ -1973,7 +2416,7 @@ static const struct cpu_option arch_opttab_armv7[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option arch_opttab_armv7_a[] = {
+static const struct cpu_arch_extension arch_opttab_armv7_a[] = {
   {
     "fp", false,
     { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
@@ -2033,7 +2476,7 @@ static const struct cpu_option arch_opttab_armv7_a[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option arch_opttab_armv7ve[] = {
+static const struct cpu_arch_extension arch_opttab_armv7ve[] = {
   {
     "vfpv3-d16", false,
     { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
@@ -2093,7 +2536,7 @@ static const struct cpu_option arch_opttab_armv7ve[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option arch_opttab_armv7_r[] = {
+static const struct cpu_arch_extension arch_opttab_armv7_r[] = {
   {
     "fp.sp", false,
     { ISA_VFPv3, isa_nobit }
@@ -2117,7 +2560,7 @@ static const struct cpu_option arch_opttab_armv7_r[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option arch_opttab_armv7e_m[] = {
+static const struct cpu_arch_extension arch_opttab_armv7e_m[] = {
   {
     "fp", false,
     { ISA_VFPv4, isa_nobit }
@@ -2137,7 +2580,7 @@ static const struct cpu_option arch_opttab_armv7e_m[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option arch_opttab_armv8_a[] = {
+static const struct cpu_arch_extension arch_opttab_armv8_a[] = {
   {
     "crc", false,
     { isa_bit_crc32, isa_nobit }
@@ -2161,7 +2604,7 @@ static const struct cpu_option arch_opttab_armv8_a[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option arch_opttab_armv8_1_a[] = {
+static const struct cpu_arch_extension arch_opttab_armv8_1_a[] = {
   {
     "simd", false,
     { ISA_FP_ARMv8,ISA_NEON, isa_nobit }
@@ -2181,7 +2624,7 @@ static const struct cpu_option arch_opttab_armv8_1_a[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option arch_opttab_armv8_2_a[] = {
+static const struct cpu_arch_extension arch_opttab_armv8_2_a[] = {
   {
     "simd", false,
     { ISA_FP_ARMv8,ISA_NEON, isa_nobit }
@@ -2205,7 +2648,7 @@ static const struct cpu_option arch_opttab_armv8_2_a[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct cpu_option arch_opttab_armv8_m_main[] = {
+static const struct cpu_arch_extension arch_opttab_armv8_m_main[] = {
   {
     "dsp", false,
     { isa_bit_ARMv7em, isa_nobit }
@@ -2225,372 +2668,340 @@ static const struct cpu_option arch_opttab_armv8_m_main[] = {
   { NULL, false, {isa_nobit}}
 };
 
-static const struct processors all_architectures[] =
+static const struct arch_option all_architectures[] =
 {
   {
-    "armv2", TARGET_CPU_arm2,
-    (TF_CO_PROC | TF_NO_MODE32),
-    "2", BASE_ARCH_2,
+    "armv2",
+    NULL,
     {
       ISA_ARMv2,isa_bit_mode26,
       isa_nobit
     },
-    NULL,
-    NULL
+    "2", BASE_ARCH_2,
+    TARGET_CPU_arm2,
   },
   {
-    "armv2a", TARGET_CPU_arm2,
-    (TF_CO_PROC | TF_NO_MODE32),
-    "2", BASE_ARCH_2,
+    "armv2a",
+    NULL,
     {
       ISA_ARMv2,isa_bit_mode26,
       isa_nobit
     },
-    NULL,
-    NULL
+    "2", BASE_ARCH_2,
+    TARGET_CPU_arm2,
   },
   {
-    "armv3", TARGET_CPU_arm6,
-    (TF_CO_PROC),
-    "3", BASE_ARCH_3,
+    "armv3",
+    NULL,
     {
       ISA_ARMv3,isa_bit_mode26,
       isa_nobit
     },
-    NULL,
-    NULL
+    "3", BASE_ARCH_3,
+    TARGET_CPU_arm6,
   },
   {
-    "armv3m", TARGET_CPU_arm7m,
-    (TF_CO_PROC),
-    "3M", BASE_ARCH_3M,
+    "armv3m",
+    NULL,
     {
       ISA_ARMv3m,isa_bit_mode26,
       isa_nobit
     },
-    NULL,
-    NULL
+    "3M", BASE_ARCH_3M,
+    TARGET_CPU_arm7m,
   },
   {
-    "armv4", TARGET_CPU_arm7tdmi,
-    (TF_CO_PROC),
-    "4", BASE_ARCH_4,
+    "armv4",
+    NULL,
     {
       ISA_ARMv4,isa_bit_mode26,
       isa_nobit
     },
-    NULL,
-    NULL
+    "4", BASE_ARCH_4,
+    TARGET_CPU_arm7tdmi,
   },
   {
-    "armv4t", TARGET_CPU_arm7tdmi,
-    (TF_CO_PROC),
-    "4T", BASE_ARCH_4T,
+    "armv4t",
+    NULL,
     {
       ISA_ARMv4t,
       isa_nobit
     },
-    NULL,
-    NULL
+    "4T", BASE_ARCH_4T,
+    TARGET_CPU_arm7tdmi,
   },
   {
-    "armv5", TARGET_CPU_arm10tdmi,
-    (TF_CO_PROC),
-    "5", BASE_ARCH_5,
+    "armv5",
+    NULL,
     {
       ISA_ARMv5,
       isa_nobit
     },
-    NULL,
-    NULL
+    "5", BASE_ARCH_5,
+    TARGET_CPU_arm10tdmi,
   },
   {
-    "armv5t", TARGET_CPU_arm10tdmi,
-    (TF_CO_PROC),
-    "5T", BASE_ARCH_5T,
+    "armv5t",
+    NULL,
     {
       ISA_ARMv5t,
       isa_nobit
     },
-    NULL,
-    NULL
+    "5T", BASE_ARCH_5T,
+    TARGET_CPU_arm10tdmi,
   },
   {
-    "armv5e", TARGET_CPU_arm1026ejs,
-    (TF_CO_PROC),
-    "5E", BASE_ARCH_5E,
+    "armv5e",
+    arch_opttab_armv5e,
     {
       ISA_ARMv5e,
       isa_nobit
     },
-    arch_opttab_armv5e,
-    NULL
+    "5E", BASE_ARCH_5E,
+    TARGET_CPU_arm1026ejs,
   },
   {
-    "armv5te", TARGET_CPU_arm1026ejs,
-    (TF_CO_PROC),
-    "5TE", BASE_ARCH_5TE,
+    "armv5te",
+    arch_opttab_armv5te,
     {
       ISA_ARMv5te,
       isa_nobit
     },
-    arch_opttab_armv5te,
-    NULL
+    "5TE", BASE_ARCH_5TE,
+    TARGET_CPU_arm1026ejs,
   },
   {
-    "armv5tej", TARGET_CPU_arm1026ejs,
-    (TF_CO_PROC),
-    "5TEJ", BASE_ARCH_5TEJ,
+    "armv5tej",
+    arch_opttab_armv5tej,
     {
       ISA_ARMv5tej,
       isa_nobit
     },
-    arch_opttab_armv5tej,
-    NULL
+    "5TEJ", BASE_ARCH_5TEJ,
+    TARGET_CPU_arm1026ejs,
   },
   {
-    "armv6", TARGET_CPU_arm1136js,
-    (TF_CO_PROC),
-    "6", BASE_ARCH_6,
+    "armv6",
+    arch_opttab_armv6,
     {
       ISA_ARMv6,
       isa_nobit
     },
-    arch_opttab_armv6,
-    NULL
+    "6", BASE_ARCH_6,
+    TARGET_CPU_arm1136js,
   },
   {
-    "armv6j", TARGET_CPU_arm1136js,
-    (TF_CO_PROC),
-    "6J", BASE_ARCH_6J,
+    "armv6j",
+    arch_opttab_armv6j,
     {
       ISA_ARMv6j,
       isa_nobit
     },
-    arch_opttab_armv6j,
-    NULL
+    "6J", BASE_ARCH_6J,
+    TARGET_CPU_arm1136js,
   },
   {
-    "armv6k", TARGET_CPU_mpcore,
-    (TF_CO_PROC),
-    "6K", BASE_ARCH_6K,
+    "armv6k",
+    arch_opttab_armv6k,
     {
       ISA_ARMv6k,
       isa_nobit
     },
-    arch_opttab_armv6k,
-    NULL
+    "6K", BASE_ARCH_6K,
+    TARGET_CPU_mpcore,
   },
   {
-    "armv6z", TARGET_CPU_arm1176jzs,
-    (TF_CO_PROC),
-    "6Z", BASE_ARCH_6Z,
+    "armv6z",
+    arch_opttab_armv6z,
     {
       ISA_ARMv6z,
       isa_nobit
     },
-    arch_opttab_armv6z,
-    NULL
+    "6Z", BASE_ARCH_6Z,
+    TARGET_CPU_arm1176jzs,
   },
   {
-    "armv6kz", TARGET_CPU_arm1176jzs,
-    (TF_CO_PROC),
-    "6KZ", BASE_ARCH_6KZ,
+    "armv6kz",
+    arch_opttab_armv6kz,
     {
       ISA_ARMv6kz,
       isa_nobit
     },
-    arch_opttab_armv6kz,
-    NULL
+    "6KZ", BASE_ARCH_6KZ,
+    TARGET_CPU_arm1176jzs,
   },
   {
-    "armv6zk", TARGET_CPU_arm1176jzs,
-    (TF_CO_PROC),
-    "6KZ", BASE_ARCH_6KZ,
+    "armv6zk",
+    arch_opttab_armv6zk,
     {
       ISA_ARMv6kz,
       isa_nobit
     },
-    arch_opttab_armv6zk,
-    NULL
+    "6KZ", BASE_ARCH_6KZ,
+    TARGET_CPU_arm1176jzs,
   },
   {
-    "armv6t2", TARGET_CPU_arm1156t2s,
-    (TF_CO_PROC),
-    "6T2", BASE_ARCH_6T2,
+    "armv6t2",
+    arch_opttab_armv6t2,
     {
       ISA_ARMv6t2,
       isa_nobit
     },
-    arch_opttab_armv6t2,
-    NULL
+    "6T2", BASE_ARCH_6T2,
+    TARGET_CPU_arm1156t2s,
   },
   {
-    "armv6-m", TARGET_CPU_cortexm1,
-    0,
-    "6M", BASE_ARCH_6M,
+    "armv6-m",
+    NULL,
     {
       ISA_ARMv6m,
       isa_nobit
     },
-    NULL,
-    NULL
+    "6M", BASE_ARCH_6M,
+    TARGET_CPU_cortexm1,
   },
   {
-    "armv6s-m", TARGET_CPU_cortexm1,
-    0,
-    "6M", BASE_ARCH_6M,
+    "armv6s-m",
+    NULL,
     {
       ISA_ARMv6m,
       isa_nobit
     },
-    NULL,
-    NULL
+    "6M", BASE_ARCH_6M,
+    TARGET_CPU_cortexm1,
   },
   {
-    "armv7", TARGET_CPU_cortexa8,
-    (TF_CO_PROC),
-    "7", BASE_ARCH_7,
+    "armv7",
+    arch_opttab_armv7,
     {
       ISA_ARMv7,
       isa_nobit
     },
-    arch_opttab_armv7,
-    NULL
+    "7", BASE_ARCH_7,
+    TARGET_CPU_cortexa8,
   },
   {
-    "armv7-a", TARGET_CPU_cortexa8,
-    (TF_CO_PROC),
-    "7A", BASE_ARCH_7A,
+    "armv7-a",
+    arch_opttab_armv7_a,
     {
       ISA_ARMv7a,
       isa_nobit
     },
-    arch_opttab_armv7_a,
-    NULL
+    "7A", BASE_ARCH_7A,
+    TARGET_CPU_cortexa8,
   },
   {
-    "armv7ve", TARGET_CPU_cortexa8,
-    (TF_CO_PROC),
-    "7A", BASE_ARCH_7A,
+    "armv7ve",
+    arch_opttab_armv7ve,
     {
       ISA_ARMv7ve,
       isa_nobit
     },
-    arch_opttab_armv7ve,
-    NULL
+    "7A", BASE_ARCH_7A,
+    TARGET_CPU_cortexa8,
   },
   {
-    "armv7-r", TARGET_CPU_cortexr4,
-    (TF_CO_PROC),
-    "7R", BASE_ARCH_7R,
+    "armv7-r",
+    arch_opttab_armv7_r,
     {
       ISA_ARMv7r,
       isa_nobit
     },
-    arch_opttab_armv7_r,
-    NULL
+    "7R", BASE_ARCH_7R,
+    TARGET_CPU_cortexr4,
   },
   {
-    "armv7-m", TARGET_CPU_cortexm3,
-    (TF_CO_PROC),
-    "7M", BASE_ARCH_7M,
+    "armv7-m",
+    NULL,
     {
       ISA_ARMv7m,
       isa_nobit
     },
-    NULL,
-    NULL
+    "7M", BASE_ARCH_7M,
+    TARGET_CPU_cortexm3,
   },
   {
-    "armv7e-m", TARGET_CPU_cortexm4,
-    (TF_CO_PROC),
-    "7EM", BASE_ARCH_7EM,
+    "armv7e-m",
+    arch_opttab_armv7e_m,
     {
       ISA_ARMv7em,
       isa_nobit
     },
-    arch_opttab_armv7e_m,
-    NULL
+    "7EM", BASE_ARCH_7EM,
+    TARGET_CPU_cortexm4,
   },
   {
-    "armv8-a", TARGET_CPU_cortexa53,
-    (TF_CO_PROC),
-    "8A", BASE_ARCH_8A,
+    "armv8-a",
+    arch_opttab_armv8_a,
     {
       ISA_ARMv8a,
       isa_nobit
     },
-    arch_opttab_armv8_a,
-    NULL
+    "8A", BASE_ARCH_8A,
+    TARGET_CPU_cortexa53,
   },
   {
-    "armv8.1-a", TARGET_CPU_cortexa53,
-    (TF_CO_PROC),
-    "8A", BASE_ARCH_8A,
+    "armv8.1-a",
+    arch_opttab_armv8_1_a,
     {
       ISA_ARMv8_1a,
       isa_nobit
     },
-    arch_opttab_armv8_1_a,
-    NULL
+    "8A", BASE_ARCH_8A,
+    TARGET_CPU_cortexa53,
   },
   {
-    "armv8.2-a", TARGET_CPU_cortexa53,
-    (TF_CO_PROC),
-    "8A", BASE_ARCH_8A,
+    "armv8.2-a",
+    arch_opttab_armv8_2_a,
     {
       ISA_ARMv8_2a,
       isa_nobit
     },
-    arch_opttab_armv8_2_a,
-    NULL
+    "8A", BASE_ARCH_8A,
+    TARGET_CPU_cortexa53,
   },
   {
-    "armv8-m.base", TARGET_CPU_cortexm23,
-    0,
-    "8M_BASE", BASE_ARCH_8M_BASE,
+    "armv8-m.base",
+    NULL,
     {
       ISA_ARMv8m_base,
       isa_nobit
     },
-    NULL,
-    NULL
+    "8M_BASE", BASE_ARCH_8M_BASE,
+    TARGET_CPU_cortexm23,
   },
   {
-    "armv8-m.main", TARGET_CPU_cortexm7,
-    (TF_CO_PROC),
-    "8M_MAIN", BASE_ARCH_8M_MAIN,
+    "armv8-m.main",
+    arch_opttab_armv8_m_main,
     {
       ISA_ARMv8m_main,
       isa_nobit
     },
-    arch_opttab_armv8_m_main,
-    NULL
+    "8M_MAIN", BASE_ARCH_8M_MAIN,
+    TARGET_CPU_cortexm7,
   },
   {
-    "iwmmxt", TARGET_CPU_iwmmxt,
-    (TF_LDSCHED | TF_STRONG | TF_XSCALE),
-    "5TE", BASE_ARCH_5TE,
+    "iwmmxt",
+    NULL,
     {
       ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,
       isa_nobit
     },
-    NULL,
-    NULL
+    "5TE", BASE_ARCH_5TE,
+    TARGET_CPU_iwmmxt,
   },
   {
-    "iwmmxt2", TARGET_CPU_iwmmxt2,
-    (TF_LDSCHED | TF_STRONG | TF_XSCALE),
-    "5TE", BASE_ARCH_5TE,
+    "iwmmxt2",
+    NULL,
     {
       ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2,
       isa_nobit
     },
-    NULL,
-    NULL
+    "5TE", BASE_ARCH_5TE,
+    TARGET_CPU_iwmmxt2,
   },
-  {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL, NULL}
+  {{NULL, NULL, {isa_nobit}},
+   NULL, BASE_ARCH_0, TARGET_CPU_arm_none}
 };
 
 const struct arm_fpu_desc all_fpus[] =
diff --git a/gcc/config/arm/arm-cpu.h b/gcc/config/arm/arm-cpu.h
index cd282db..d36ccb9 100644
--- a/gcc/config/arm/arm-cpu.h
+++ b/gcc/config/arm/arm-cpu.h
@@ -135,6 +135,44 @@ enum processor_type
   TARGET_CPU_arm_none
 };
 
+enum arch_type
+{
+  TARGET_ARCH_armv2,
+  TARGET_ARCH_armv2a,
+  TARGET_ARCH_armv3,
+  TARGET_ARCH_armv3m,
+  TARGET_ARCH_armv4,
+  TARGET_ARCH_armv4t,
+  TARGET_ARCH_armv5,
+  TARGET_ARCH_armv5t,
+  TARGET_ARCH_armv5e,
+  TARGET_ARCH_armv5te,
+  TARGET_ARCH_armv5tej,
+  TARGET_ARCH_armv6,
+  TARGET_ARCH_armv6j,
+  TARGET_ARCH_armv6k,
+  TARGET_ARCH_armv6z,
+  TARGET_ARCH_armv6kz,
+  TARGET_ARCH_armv6zk,
+  TARGET_ARCH_armv6t2,
+  TARGET_ARCH_armv6_m,
+  TARGET_ARCH_armv6s_m,
+  TARGET_ARCH_armv7,
+  TARGET_ARCH_armv7_a,
+  TARGET_ARCH_armv7ve,
+  TARGET_ARCH_armv7_r,
+  TARGET_ARCH_armv7_m,
+  TARGET_ARCH_armv7e_m,
+  TARGET_ARCH_armv8_a,
+  TARGET_ARCH_armv8_1_a,
+  TARGET_ARCH_armv8_2_a,
+  TARGET_ARCH_armv8_m_base,
+  TARGET_ARCH_armv8_m_main,
+  TARGET_ARCH_iwmmxt,
+  TARGET_ARCH_iwmmxt2,
+  TARGET_ARCH_arm_none
+};
+
 enum fpu_type
 {
   TARGET_FPU_vfp,
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index cf8b437..ada2503 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -462,8 +462,6 @@ struct arm_build_target
   const char *arch_name;
   /* Preprocessor substring (never NULL).  */
   const char *arch_pp_name;
-  /* CPU identifier for the core we're compiling for (architecturally).  */
-  enum processor_type arch_core;
   /* The base architecture value.  */
   enum base_architecture base_arch;
   /* Bitmap encapsulating the isa_bits for the target environment.  */
@@ -478,5 +476,41 @@ struct arm_build_target
 
 extern struct arm_build_target arm_active_target;
 
+struct cpu_arch_extension
+{
+  const char *const name;
+  bool remove;
+  const enum isa_feature isa_bits[isa_num_bits];
+};
+
+struct cpu_arch_option
+{
+  /* Name for this option.  */
+  const char *name;
+  /* List of feature extensions permitted.  */
+  const struct cpu_arch_extension *extensions;
+  /* Standard feature bits.  */
+  enum isa_feature isa_bits[isa_num_bits];
+};
+
+struct arch_option
+{
+  /* Common option fields.  */
+  cpu_arch_option common;
+  /* Short string for this architecture.  */
+  const char *arch;
+  /* Base architecture, from which this specific architecture is derived.  */
+  enum base_architecture base_arch;
+  /* Default tune target (in the absence of any more specific data).  */
+  enum processor_type tune_id;
+};
+
+struct cpu_option
+{
+  /* Common option fields.  */
+  cpu_arch_option common;
+  /* Architecture upon which this CPU is based.  */
+  enum arch_type arch;
+};
 
 #endif /* ! GCC_ARM_PROTOS_H */
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index afb4a4b..5664145 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -975,26 +975,13 @@ int arm_regs_in_sequence[] =
 
 /* Initialization code.  */
 
-struct cpu_option
+struct cpu_tune
 {
-  const char *const name;
-  bool remove;
-  const enum isa_feature isa_bits[isa_num_bits];
-};
-
-struct processors
-{
-  const char *const name;
-  enum processor_type core;
+  enum processor_type scheduler;
   unsigned int tune_flags;
-  const char *arch;
-  enum base_architecture base_arch;
-  const enum isa_feature isa_bits[isa_num_bits];
-  const struct cpu_option* const opttab;
-  const struct tune_params *const tune;
+  const struct tune_params *tune;
 };
 
-
 #define ARM_PREFETCH_NOT_BENEFICIAL { 0, -1, -1 }
 #define ARM_PREFETCH_BENEFICIAL(num_slots,l1_size,l1_line_size) \
   {								\
@@ -3069,15 +3056,59 @@ arm_initialize_isa (sbitmap isa, const enum isa_feature *isa_bits)
     bitmap_set_bit (isa, *(isa_bits++));
 }
 
-/* List the premitted CPU or architecture names.  If TARGET is a near
+/* List the premitted CPU option names.  If TARGET is a near miss for an
+   entry, print out the suggested alternative.  */
+static void
+arm_print_hint_for_cpu_option (const char *target,
+			       const cpu_option *list)
+{
+  auto_vec<const char*> candidates;
+  for (; list->common.name != NULL; list++)
+    candidates.safe_push (list->common.name);
+  char *s;
+  const char *hint = candidates_list_and_hint (target, s, candidates);
+  if (hint)
+    inform (input_location, "valid arguments are: %s; did you mean %qs?",
+	    s, hint);
+  else
+    inform (input_location, "valid arguments are: %s", s);
+
+  XDELETEVEC (s);
+}
+
+/* Parse the base component of a CPU selection in LIST.  Return a
+   pointer to the entry in the architecture table.  OPTNAME is the
+   name of the option we are parsing and can be used if a diagnostic
+   is needed.  */
+static const cpu_option *
+arm_parse_cpu_option_name (const cpu_option *list, const char *optname,
+		       const char *target)
+{
+  const cpu_option *entry;
+  const char *end  = strchr (target, '+');
+  size_t len = end ? end - target : strlen (target);
+
+  for (entry = list; entry->common.name != NULL; entry++)
+    {
+      if (strncmp (entry->common.name, target, len) == 0
+	  && entry->common.name[len] == '\0')
+	return entry;
+    }
+
+  error_at (input_location, "unrecognized %s target: %s", optname, target);
+  arm_print_hint_for_cpu_option (target, list);
+  return NULL;
+}
+
+/* List the premitted architecture option names.  If TARGET is a near
    miss for an entry, print out the suggested alternative.  */
 static void
-arm_print_hint_for_core_or_arch (const char *target,
-				 const struct processors *list)
+arm_print_hint_for_arch_option (const char *target,
+			       const arch_option *list)
 {
   auto_vec<const char*> candidates;
-  for (; list->name != NULL; list++)
-    candidates.safe_push (list->name);
+  for (; list->common.name != NULL; list++)
+    candidates.safe_push (list->common.name);
   char *s;
   const char *hint = candidates_list_and_hint (target, s, candidates);
   if (hint)
@@ -3093,23 +3124,23 @@ arm_print_hint_for_core_or_arch (const char *target,
    LIST.  Return a pointer to the entry in the architecture table.
    OPTNAME is the name of the option we are parsing and can be used if
    a diagnostic is needed.  */
-static const struct processors *
-arm_parse_arch_cpu_name (const struct processors *list, const char *optname,
-			 const char *target)
+static const arch_option *
+arm_parse_arch_option_name (const arch_option *list, const char *optname,
+			    const char *target)
 {
-  const struct processors *entry;
+  const arch_option *entry;
   const char *end  = strchr (target, '+');
   size_t len = end ? end - target : strlen (target);
 
-  for (entry = list; entry->name != NULL; entry++)
+  for (entry = list; entry->common.name != NULL; entry++)
     {
-      if (strncmp (entry->name, target, len) == 0
-	  && entry->name[len] == '\0')
+      if (strncmp (entry->common.name, target, len) == 0
+	  && entry->common.name[len] == '\0')
 	return entry;
     }
 
   error_at (input_location, "unrecognized %s target: %s", optname, target);
-  arm_print_hint_for_core_or_arch (target, list);
+  arm_print_hint_for_arch_option (target, list);
   return NULL;
 }
 
@@ -3118,7 +3149,7 @@ arm_parse_arch_cpu_name (const struct processors *list, const char *optname,
    values.  */
 static void
 arm_unrecognized_feature (const char *opt, size_t len,
-			  const struct processors *target)
+			  const cpu_arch_option *target)
 {
   char *this_opt = XALLOCAVEC (char, len+1);
   auto_vec<const char*> candidates;
@@ -3128,7 +3159,9 @@ arm_unrecognized_feature (const char *opt, size_t len,
 
   error_at (input_location, "%qs does not support feature %qs", target->name,
 	    this_opt);
-  for (const cpu_option *list = target->opttab; list->name != NULL; list++)
+  for (const cpu_arch_extension *list = target->extensions;
+       list->name != NULL;
+       list++)
     candidates.safe_push (list->name);
 
   char *s;
@@ -3146,15 +3179,15 @@ arm_unrecognized_feature (const char *opt, size_t len,
 /* Parse any feature extensions to add to (or remove from) the
    permitted ISA selection.  */
 static void
-arm_parse_arch_cpu_features (sbitmap isa, const struct processors *target,
-			     const char *opts_in)
+arm_parse_option_features (sbitmap isa, const cpu_arch_option *target,
+			   const char *opts_in)
 {
   const char *opts = opts_in;
 
   if (!opts)
     return;
 
-  if (!target->opttab)
+  if (!target->extensions)
     {
       error_at (input_location, "%s does not take any feature options",
 		target->name);
@@ -3164,12 +3197,14 @@ arm_parse_arch_cpu_features (sbitmap isa, const struct processors *target,
   while (opts)
     {
       gcc_assert (*opts == '+');
-      const struct cpu_option *entry;
+      const struct cpu_arch_extension *entry;
       const char *end = strchr (++opts, '+');
       size_t len = end ? end - opts : strlen (opts);
       bool matched = false;
 
-      for (entry = target->opttab; !matched && entry->name != NULL; entry++)
+      for (entry = target->extensions;
+	   !matched && entry->name != NULL;
+	   entry++)
 	{
 	  if (strncmp (entry->name, opts, len) == 0
 	      && entry->name[len] == '\0')
@@ -3211,10 +3246,10 @@ arm_configure_build_target (struct arm_build_target *target,
 			    struct gcc_options *opts_set,
 			    bool warn_compatible)
 {
-  const struct processors *arm_selected_tune = NULL;
-  const struct processors *arm_selected_arch = NULL;
-  const struct processors *arm_selected_cpu = NULL;
-  const struct arm_fpu_desc *arm_selected_fpu = NULL;
+  const cpu_option *arm_selected_tune = NULL;
+  const arch_option *arm_selected_arch = NULL;
+  const cpu_option *arm_selected_cpu = NULL;
+  const arm_fpu_desc *arm_selected_fpu = NULL;
   const char *tune_opts = NULL;
   const char *arch_opts = NULL;
   const char *cpu_opts = NULL;
@@ -3225,16 +3260,16 @@ arm_configure_build_target (struct arm_build_target *target,
 
   if (opts_set->x_arm_arch_string)
     {
-      arm_selected_arch = arm_parse_arch_cpu_name (all_architectures,
-						   "-march",
-						   opts->x_arm_arch_string);
+      arm_selected_arch = arm_parse_arch_option_name (all_architectures,
+						      "-march",
+						      opts->x_arm_arch_string);
       arch_opts = strchr (opts->x_arm_arch_string, '+');
     }
 
   if (opts_set->x_arm_cpu_string)
     {
-      arm_selected_cpu = arm_parse_arch_cpu_name (all_cores, "-mcpu",
-						  opts->x_arm_cpu_string);
+      arm_selected_cpu = arm_parse_cpu_option_name (all_cores, "-mcpu",
+						    opts->x_arm_cpu_string);
       cpu_opts = strchr (opts->x_arm_cpu_string, '+');
       arm_selected_tune = arm_selected_cpu;
       /* If taking the tuning from -mcpu, we don't need to rescan the
@@ -3243,22 +3278,24 @@ arm_configure_build_target (struct arm_build_target *target,
 
   if (opts_set->x_arm_tune_string)
     {
-      arm_selected_tune = arm_parse_arch_cpu_name (all_cores, "-mtune",
-						   opts->x_arm_tune_string);
+      arm_selected_tune = arm_parse_cpu_option_name (all_cores, "-mtune",
+						     opts->x_arm_tune_string);
       tune_opts = strchr (opts->x_arm_tune_string, '+');
     }
 
   if (arm_selected_arch)
     {
-      arm_initialize_isa (target->isa, arm_selected_arch->isa_bits);
-      arm_parse_arch_cpu_features (target->isa, arm_selected_arch, arch_opts);
+      arm_initialize_isa (target->isa, arm_selected_arch->common.isa_bits);
+      arm_parse_option_features (target->isa, &arm_selected_arch->common,
+				 arch_opts);
 
       if (arm_selected_cpu)
 	{
 	  auto_sbitmap cpu_isa (isa_num_bits);
 
-	  arm_initialize_isa (cpu_isa, arm_selected_cpu->isa_bits);
-	  arm_parse_arch_cpu_features (cpu_isa, arm_selected_cpu, cpu_opts);
+	  arm_initialize_isa (cpu_isa, arm_selected_cpu->common.isa_bits);
+	  arm_parse_option_features (cpu_isa, &arm_selected_cpu->common,
+				     cpu_opts);
 	  bitmap_xor (cpu_isa, cpu_isa, target->isa);
 	  /* Ignore any bits that are quirk bits.  */
 	  bitmap_and_compl (cpu_isa, cpu_isa, isa_quirkbits);
@@ -3269,47 +3306,51 @@ arm_configure_build_target (struct arm_build_target *target,
 	    {
 	      if (warn_compatible)
 		warning (0, "switch -mcpu=%s conflicts with -march=%s switch",
-			 arm_selected_cpu->name, arm_selected_arch->name);
+			 arm_selected_cpu->common.name,
+			 arm_selected_arch->common.name);
 	      /* -march wins for code generation.
 		 -mcpu wins for default tuning.  */
 	      if (!arm_selected_tune)
 		arm_selected_tune = arm_selected_cpu;
 
-	      arm_selected_cpu = arm_selected_arch;
-	      target->arch_name = arm_selected_arch->name;
+	      arm_selected_cpu = all_cores + arm_selected_arch->tune_id;
+	      target->arch_name = arm_selected_arch->common.name;
 	    }
 	  else
 	    {
 	      /* Architecture and CPU are essentially the same.
 		 Prefer the CPU setting.  */
-	      arm_selected_arch = NULL;
-	      target->core_name = arm_selected_cpu->name;
+	      arm_selected_arch = all_architectures + arm_selected_cpu->arch;
+	      target->core_name = arm_selected_cpu->common.name;
 	    }
 	}
       else
 	{
 	  /* Pick a CPU based on the architecture.  */
-	  arm_selected_cpu = arm_selected_arch;
-	  target->arch_name = arm_selected_arch->name;
+	  arm_selected_cpu = all_cores + arm_selected_arch->tune_id;
+	  target->arch_name = arm_selected_arch->common.name;
 	  /* Note: target->core_name is left unset in this path.  */
 	}
     }
   else if (arm_selected_cpu)
     {
-      target->core_name = arm_selected_cpu->name;
-      arm_initialize_isa (target->isa, arm_selected_cpu->isa_bits);
-      arm_parse_arch_cpu_features (target->isa, arm_selected_cpu, cpu_opts);
+      target->core_name = arm_selected_cpu->common.name;
+      arm_initialize_isa (target->isa, arm_selected_cpu->common.isa_bits);
+      arm_parse_option_features (target->isa, &arm_selected_cpu->common,
+				 cpu_opts);
+      arm_selected_arch = all_architectures + arm_selected_cpu->arch;
     }
-  /* If the user did not specify a processor, choose one for them.  */
+  /* If the user did not specify a processor or architecture, choose
+     one for them.  */
   else
     {
-      const struct processors * sel;
+      const cpu_option *sel;
       auto_sbitmap sought_isa (isa_num_bits);
       bitmap_clear (sought_isa);
       auto_sbitmap default_isa (isa_num_bits);
 
       arm_selected_cpu = &all_cores[TARGET_CPU_DEFAULT];
-      gcc_assert (arm_selected_cpu->name);
+      gcc_assert (arm_selected_cpu->common.name);
 
       /* RWE: All of the selection logic below (to the end of this
 	 'if' clause) looks somewhat suspect.  It appears to be mostly
@@ -3318,7 +3359,7 @@ arm_configure_build_target (struct arm_build_target *target,
 	 user might be expecting).  I think it should be removed once
 	 support for the pre-thumb era cores is removed.  */
       sel = arm_selected_cpu;
-      arm_initialize_isa (default_isa, sel->isa_bits);
+      arm_initialize_isa (default_isa, sel->common.isa_bits);
 
       /* Now check to see if the user has specified any command line
 	 switches that require certain abilities from the cpu.  */
@@ -3351,18 +3392,18 @@ arm_configure_build_target (struct arm_build_target *target,
 	  /* Try to locate a CPU type that supports all of the abilities
 	     of the default CPU, plus the extra abilities requested by
 	     the user.  */
-	  for (sel = all_cores; sel->name != NULL; sel++)
+	  for (sel = all_cores; sel->common.name != NULL; sel++)
 	    {
-	      arm_initialize_isa (candidate_isa, sel->isa_bits);
+	      arm_initialize_isa (candidate_isa, sel->common.isa_bits);
 	      /* An exact match?  */
 	      if (bitmap_equal_p (default_isa, candidate_isa))
 		break;
 	    }
 
-	  if (sel->name == NULL)
+	  if (sel->common.name == NULL)
 	    {
 	      unsigned current_bit_count = isa_num_bits;
-	      const struct processors * best_fit = NULL;
+	      const cpu_option *best_fit = NULL;
 
 	      /* Ideally we would like to issue an error message here
 		 saying that it was not possible to find a CPU compatible
@@ -3376,9 +3417,9 @@ arm_configure_build_target (struct arm_build_target *target,
 		 command line options we scan the array again looking
 		 for a best match.  The best match must have at least
 		 the capabilities of the perfect match.  */
-	      for (sel = all_cores; sel->name != NULL; sel++)
+	      for (sel = all_cores; sel->common.name != NULL; sel++)
 		{
-		  arm_initialize_isa (candidate_isa, sel->isa_bits);
+		  arm_initialize_isa (candidate_isa, sel->common.isa_bits);
 
 		  if (bitmap_subset_p (default_isa, candidate_isa))
 		    {
@@ -3404,11 +3445,13 @@ arm_configure_build_target (struct arm_build_target *target,
 
       /* Now we know the CPU, we can finally initialize the target
 	 structure.  */
-      target->core_name = arm_selected_cpu->name;
-      arm_initialize_isa (target->isa, arm_selected_cpu->isa_bits);
+      target->core_name = arm_selected_cpu->common.name;
+      arm_initialize_isa (target->isa, arm_selected_cpu->common.isa_bits);
+      arm_selected_arch = all_architectures + arm_selected_cpu->arch;
     }
 
   gcc_assert (arm_selected_cpu);
+  gcc_assert (arm_selected_arch);
 
   if (opts->x_arm_fpu_index != TARGET_FPU_auto)
     {
@@ -3420,20 +3463,20 @@ arm_configure_build_target (struct arm_build_target *target,
       bitmap_ior (target->isa, target->isa, fpu_bits);
     }
 
-  /* The selected cpu may be an architecture, so lookup tuning by core ID.  */
   if (!arm_selected_tune)
-    arm_selected_tune = &all_cores[arm_selected_cpu->core];
+    arm_selected_tune = arm_selected_cpu;
   else /* Validate the features passed to -mtune.  */
-    arm_parse_arch_cpu_features (NULL, arm_selected_tune, tune_opts);
+    arm_parse_option_features (NULL, &arm_selected_tune->common, tune_opts);
+
+  const cpu_tune *tune_data = &all_tunes[arm_selected_tune - all_cores];
 
   /* Finish initializing the target structure.  */
-  target->arch_pp_name = arm_selected_cpu->arch;
-  target->base_arch = arm_selected_cpu->base_arch;
-  target->arch_core = arm_selected_cpu->core;
+  target->arch_pp_name = arm_selected_arch->arch;
+  target->base_arch = arm_selected_arch->base_arch;
 
-  target->tune_flags = arm_selected_tune->tune_flags;
-  target->tune = arm_selected_tune->tune;
-  target->tune_core = arm_selected_tune->core;
+  target->tune_flags = tune_data->tune_flags;
+  target->tune = tune_data->tune;
+  target->tune_core = tune_data->scheduler;
 }
 
 /* Fix up any incompatible options that the user has specified.  */
@@ -26299,18 +26342,20 @@ arm_print_tune_info (void)
 static void
 arm_print_asm_arch_directives ()
 {
-  const struct processors *arch
-    = arm_parse_arch_cpu_name (all_architectures, "-march",
-			       arm_active_target.arch_name);
+  const arch_option *arch
+    = arm_parse_arch_option_name (all_architectures, "-march",
+				  arm_active_target.arch_name);
   auto_sbitmap opt_bits (isa_num_bits);
 
   gcc_assert (arch);
 
   asm_fprintf (asm_out_file, "\t.arch %s\n", arm_active_target.arch_name);
-  if (!arch->opttab)
+  if (!arch->common.extensions)
     return;
 
-  for (const struct cpu_option *opt = arch->opttab; opt->name != NULL; opt++)
+  for (const struct cpu_arch_extension *opt = arch->common.extensions;
+       opt->name != NULL;
+       opt++)
     {
       if (!opt->remove)
 	{
diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk
index c95d922..57565bd 100644
--- a/gcc/config/arm/parsecpu.awk
+++ b/gcc/config/arm/parsecpu.awk
@@ -102,6 +102,17 @@ function gen_headers () {
     print "  TARGET_CPU_arm_none"
     print "};\n"
 
+    print "enum arch_type"
+    print "{"
+
+    narchs = split (arch_list, archs)
+
+    for (n = 1; n <= narchs; n++) {
+	print "  TARGET_ARCH_"arch_cnames[archs[n]]","
+    }
+    print "  TARGET_ARCH_arm_none"
+    print "};\n"
+
     print "enum fpu_type"
     print "{"
 
@@ -121,7 +132,7 @@ function gen_data () {
 
     for (n = 1; n <= ncpus; n++) {
 	if (cpus[n] in cpu_opts) {
-	    print "static const struct cpu_option cpu_opttab_" \
+	    print "static const cpu_arch_extension cpu_opttab_" \
 		cpu_cnames[cpus[n]] "[] = {"
 	    nopts = split (cpu_opts[cpus[n]], opts)
 	    for (opt = 1; opt <= nopts; opt++) {
@@ -136,32 +147,25 @@ function gen_data () {
 	}
     }
 
-    print "static const struct processors all_cores[] ="
+    print "static const cpu_option all_cores[] ="
     print "{"
 
     for (n = 1; n <= ncpus; n++) {
 	print "  {"
-	print "    \"" cpus[n] "\","
-	if (cpus[n] in cpu_tune_for) {
-	    if (! (cpu_tune_for[cpus[n]] in cpu_cnames)) {
-		fatal("unknown \"tune for\" target " cpu_tune_for[cpus[n]] \
-		      " for CPU " cpus[n])
-	    }
-	    print "    TARGET_CPU_" cpu_cnames[cpu_tune_for[cpus[n]]] ","
-	} else {
-	    print "    TARGET_CPU_" cpu_cnames[cpus[n]] ","
-	}
-	if (cpus[n] in cpu_tune_flags) {
-	    print "    (" cpu_tune_flags[cpus[n]] "),"
-	} else print "    0,"
+	print "    {"
+	# common.name
+	print "      \"" cpus[n] "\","
+	# common.extensions
+	if (cpus[n] in cpu_opts) {
+	    print "      cpu_opttab_" cpu_cnames[cpus[n]] ","
+	} else print "      NULL,"
+	# common.isa_bits
 	nfeats = split (cpu_arch[cpus[n]], feats, "+")
 	if (! (feats[1] in arch_isa)) {
 	    fatal("unknown arch " feats[1] " for cpu " cpus[n])
 	}
-	print "    \"" arch_base[feats[1]] "\", BASE_ARCH_" \
-	    arch_base[feats[1]] ","
-	print "    {"
-	print "      " arch_isa[feats[1]] ","
+	print "      {"
+	print "        " arch_isa[feats[1]] ","
 	for (m = 2; m <= nfeats; m++) {
 	    if (! ((feats[1], feats[m]) in arch_opt_isa)) {
 		fatal("unknown feature " feats[m] " for architecture " feats[1])
@@ -169,28 +173,52 @@ function gen_data () {
 	    if (arch_opt_remove[feats[1],feats[m]] == "true") {
 		fatal("cannot remove features from architecture specs")
 	    }
-	    print "      " arch_opt_isa[feats[1],feats[m]] ","
+	    print "        " arch_opt_isa[feats[1],feats[m]] ","
 	}
-	if (cpus[n] in cpu_fpu) print "      " fpu_isa[cpu_fpu[cpus[n]]] ","
-	if (cpus[n] in cpu_isa) print "      " cpu_isa[cpus[n]] ","
-	print "      isa_nobit"
+	if (cpus[n] in cpu_fpu) print "        " fpu_isa[cpu_fpu[cpus[n]]] ","
+	if (cpus[n] in cpu_isa) print "        " cpu_isa[cpus[n]] ","
+	print "        isa_nobit"
+	print "      }"
 	print "    },"
-	if (cpus[n] in cpu_opts) {
-	    print "    cpu_opttab_" cpu_cnames[cpus[n]] ","
-	} else print "    NULL,"
-	print "    &arm_" cpu_cost[cpus[n]] "_tune"
+	# arch
+	print "    TARGET_ARCH_" arch_cnames[feats[1]]
 	print "  },"
     }
 
-    print "  {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0," \
-	" {isa_nobit}, NULL, NULL}"
-    print "};\n"
+    print "  {{NULL, NULL, {isa_nobit}}, TARGET_ARCH_arm_none}"
+    print "};"
 
+    print "static const cpu_tune all_tunes[] ="
+    print "{"
+
+    for (n = 1; n <= ncpus; n++) {
+	print "  { /* " cpus[n] ".  */"
+	# scheduler
+	if (cpus[n] in cpu_tune_for) {
+	    if (! (cpu_tune_for[cpus[n]] in cpu_cnames)) {
+		fatal("unknown \"tune for\" target " cpu_tune_for[cpus[n]] \
+		      " for CPU " cpus[n])
+	    }
+	    print "    TARGET_CPU_" cpu_cnames[cpu_tune_for[cpus[n]]] ","
+	} else {
+	    print "    TARGET_CPU_" cpu_cnames[cpus[n]] ","
+	}
+	# tune_flags
+	if (cpus[n] in cpu_tune_flags) {
+	    print "    (" cpu_tune_flags[cpus[n]] "),"
+	} else print "    0,"
+	# tune
+	print "    &arm_" cpu_cost[cpus[n]] "_tune"
+	print "  },"
+    }
+    print "  {TARGET_CPU_arm_none, 0, NULL}"
+    print "};"
+    
     narchs = split (arch_list, archs)
 
     for (n = 1; n <= narchs; n++) {
 	if (archs[n] in arch_opts) {
-	    print "static const struct cpu_option arch_opttab_" \
+	    print "static const struct cpu_arch_extension arch_opttab_" \
 		arch_cnames[archs[n]] "[] = {"
 	    nopts = split (arch_opts[archs[n]], opts)
 	    for (opt = 1; opt <= nopts; opt++) {
@@ -205,7 +233,7 @@ function gen_data () {
 	}
     }
 
-    print "static const struct processors all_architectures[] ="
+    print "static const struct arch_option all_architectures[] ="
     print "{"
 
     for (n = 1; n <= narchs; n++) {
@@ -214,26 +242,27 @@ function gen_data () {
 	    fatal("unknown \"tune for\" target " arch_tune_for[archs[n]] \
 		  " for architecture " archs[n])
 	}
-	print "    \"" archs[n] \
-	    "\", TARGET_CPU_" cpu_cnames[arch_tune_for[archs[n]]] ","
-	if (archs[n] in arch_tune_flags) {
-	    print "    (" arch_tune_flags[archs[n]] "),"
-	} else print "    0,"
-	print "    \"" arch_base[archs[n]] "\", BASE_ARCH_" \
-	    arch_base[archs[n]] ","
+	# common.name
+	print "    \"" archs[n] "\","
+	# common.extensions
+	if (archs[n] in arch_opts) {
+	    print "    arch_opttab_" arch_cnames[archs[n]] ","
+	} else print "    NULL,"
+	# common.isa_bits
 	print "    {"
 	print "      " arch_isa[archs[n]] ","
 	print "      isa_nobit"
 	print "    },"
-	if (archs[n] in arch_opts) {
-	    print "    arch_opttab_" arch_cnames[archs[n]] ","
-	} else print "    NULL,"
-	print "    NULL"
+	# arch, base_arch
+	print "    \"" arch_base[archs[n]] "\", BASE_ARCH_" \
+	    arch_base[archs[n]] ","
+	# tune_id
+	print "    TARGET_CPU_" cpu_cnames[arch_tune_for[archs[n]]] ","
 	print "  },"
     }
 
-    print "  {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0," \
-	" {isa_nobit}, NULL, NULL}"
+    print "  {{NULL, NULL, {isa_nobit}},"
+    print "   NULL, BASE_ARCH_0, TARGET_CPU_arm_none}"
     print "};\n"
 
     print "const struct arm_fpu_desc all_fpus[] ="
