From patchwork Fri Jun 9 12:53:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw (lists)" X-Patchwork-Id: 773899 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wkjDj4Nzdz9s74 for ; Fri, 9 Jun 2017 23:04:37 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="t0XoJNVI"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references:mime-version:content-type; q=dns; s= default; b=d3W3dm69bCgBCou9xCvJ3+DbfSYtF/fRP5JqxO3JUHzh3k5KCSxai +b7t+crXDh4jmHmTPzVAFk3be7jENnKDW9pFW8fZ832ehFe1cqTdv0Q8j+VkAEqB ANPdp10sy9KBUq3jliM4on2pdtKuJIvsmYo8DXABoOOjnPnka++GkY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references:mime-version:content-type; s=default; bh=LSvBLGCKSoHSK5pcrNRNaLutkcU=; b=t0XoJNVIJ7HhsHSMaZlBL3LF4ZjE 1J0GKEqxVOnEETMPjDs8rPrEnpBSELj2o6s5DKoIXNEbBSyhTLC37tfxT6/QuGi8 wiw3Zi+yV1B2g81fzrgF5kVMYf9yO8irOBQOJdsXKdvne8Ynes1ahzePXD5TwFBh SJgoo+T0nhEreMQ= Received: (qmail 100781 invoked by alias); 9 Jun 2017 12:55:02 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 91361 invoked by uid 89); 9 Jun 2017 12:54:50 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_SOFTFAIL autolearn=ham version=3.3.2 spammy=1199 X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 09 Jun 2017 12:54:47 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dJJQi-0007bh-Fg for gcc-patches@gcc.gnu.org; Fri, 09 Jun 2017 08:54:21 -0400 Received: from foss.arm.com ([217.140.101.70]:47128) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dJJQi-0007Te-5V for gcc-patches@gcc.gnu.org; Fri, 09 Jun 2017 08:54:20 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CEF202B; Fri, 9 Jun 2017 05:54:19 -0700 (PDT) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5DB713F3E1; Fri, 9 Jun 2017 05:54:19 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH 15/30] [arm] Make -mfloat-abi=softfp work when there are no FPU instructions Date: Fri, 9 Jun 2017 13:53:44 +0100 Message-Id: <50a309e2716dc50e5527a34ad8429b88e41c7919.1497004220.git.Richard.Earnshaw@arm.com> In-Reply-To: References: In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Before this patch series it wasn't really possible to not have an FPU; it was always there, even if the hardware didn't really support it. Now that we have -mfpu=auto, the concept of not having an FPU becomes real. Consequently, when the -mfloat-abi switch is set to softfp doing the Right Thing is much more important. In this case we have a soft-float ABI, but can use FP instructions if they are available. To support this we have to separate out TARGET_HARD_FLOAT into two use cases: one where the instructions exist and one when they don't. We preserve the original meaning of TARGET_HARD_FLOAT (but add an extra check) of meaning that we are generating HW FP instructions, and add a new macro for the special case when use of FP instructions is permitted, but might not be available at this time (the distinction is important because they might be enabled by an attribute during the compilation). TARGET_SOFT_FLOAT continues to be the exact inverse of TARGET_HARD_FLOAT, but we now define it as such. * config/arm/arm.h (TARGET_HARD_FLOAT): Also check that we have some floating-point instructions. (TARGET_SOFT_FLOAT): Define as inverse of TARGET_HARD_FLOAT. (TARGET_MAYBE_HARD_FLOAT): New macro. * config/arm/arm-builtins.c (arm_init_builtins): Use TARGET_MAYBE_HARD_FLOAT. * config/arm/arm.c (arm_option_override): Use TARGET_HARD_FLOAT_ABI. --- gcc/config/arm/arm-builtins.c | 4 ++-- gcc/config/arm/arm.c | 3 +-- gcc/config/arm/arm.h | 9 +++++++-- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index a0569ed..9755189 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -1876,7 +1876,7 @@ arm_init_builtins (void) arm_init_neon_builtins which uses it. */ arm_init_fp16_builtins (); - if (TARGET_HARD_FLOAT) + if (TARGET_MAYBE_HARD_FLOAT) { arm_init_neon_builtins (); arm_init_vfp_builtins (); @@ -1885,7 +1885,7 @@ arm_init_builtins (void) arm_init_acle_builtins (); - if (TARGET_HARD_FLOAT) + if (TARGET_MAYBE_HARD_FLOAT) { tree ftype_set_fpscr = build_function_type_list (void_type_node, unsigned_type_node, NULL); diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 7296ad3..97d2fbd 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3467,8 +3467,7 @@ arm_option_override (void) { if (arm_abi == ARM_ABI_IWMMXT) arm_pcs_default = ARM_PCS_AAPCS_IWMMXT; - else if (arm_float_abi == ARM_FLOAT_ABI_HARD - && TARGET_HARD_FLOAT) + else if (TARGET_HARD_FLOAT_ABI) { arm_pcs_default = ARM_PCS_AAPCS_VFP; if (!bitmap_bit_p (arm_active_target.isa, isa_bit_VFPv2)) diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index dea3d0a..570bcd7 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -119,9 +119,14 @@ extern tree arm_fp16_type_node; #define TARGET_32BIT_P(flags) (TARGET_ARM_P (flags) || TARGET_THUMB2_P (flags)) /* Run-time Target Specification. */ -#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT) /* Use hardware floating point instructions. */ -#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) +#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT \ + && bitmap_bit_p (arm_active_target.isa, \ + isa_bit_VFPv2)) +#define TARGET_SOFT_FLOAT (!TARGET_HARD_FLOAT) +/* User has permitted use of FP instructions, if they exist for this + target. */ +#define TARGET_MAYBE_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) /* Use hardware floating point calling convention. */ #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) #define TARGET_IWMMXT (arm_arch_iwmmxt)