Message ID | 50C10C2E.4010909@redhat.com |
---|---|
State | New |
Headers | show |
On Thu, Dec 06, 2012 at 04:20:46PM -0500, Vladimir Makarov wrote: > LRA should have change spilled pseudo 199 to memory. LRA did not do > that because the insn is in list of insns used by pseudo 199. This > might happen only when the insn is not recognized. > > The following patch fixes the bug. > > Committed as rev. 194270. > > 2012-12-06 Vladimir Makarov <vmakarov@redhat.com> > > * rtl.h (SUBREG_MATCH_RELOAD_P): Rename to LRA_SUBREG_P. > * recog.c (register_operand): Check LRA_SUBREG_P. > * lra-constraints.c (match_reload, simplify_operand_subreg): Use > LRA_SUBREG_P. > (emit_spill_move): Set up LRA_SUBREG_P. Yes this fixes the bug and allows a bootstrap. Thanks. Note, the fortran compiler in your branch is buggy, and I get a lot of failures when doing a make check. I don't get similar failures on today's branch (not using LRA).
On Thu, Dec 06, 2012 at 04:20:46PM -0500, Vladimir Makarov wrote:
> The following patch fixes the bug.
I decided to try and build all of Spec 2006 with LRA. All 30 benchmarks build
with the LRA branch compiler if I use -fno-lra. If I use -flra, 8 benchmarks
no longer build at -O3 -mcpu=power7. There are 3 classes of failure.
The first failure dies in gen_add2_insn:
1) gobmk
2) h264ref
3) xalancbmk
The second failure is 'Max. number of generated reload insns per insn is achieved (90):'
1) astar
2) povray
The third failure is 'internal compiler error: in check_rtl, at lra.c:2010'
1) gamess
2) dealII
3) wrf
I looked at gobmk, and I'll include the .i file in the message. It is dying
on a movti insn, where the address is a TOC relocation that has been split and
uses an unspec for the relocation. The standard add insn doesn't support this,
but there are add recognizers for this case. I can imagine we can add a PPC
specific constraint for this and use it in add{di,si}3 if we need to.
(gdb) r -O2 -quiet -mcpu=power7 -ftree-vectorize -g -da play_ascii.i
The program being debugged has been started already.
Start it from the beginning? (y or n) y
Starting program: /data/meissner/fsf-build-x86_64/lra-powerpc64-linux/gcc/cc1 -O2 -quiet -mcpu=power7 -ftree-vectorize -g -da play_ascii.i
Breakpoint 1, fancy_abort (file=0xda8850 "/home/meissner/fsf-src/lra/gcc/optabs.c", line=4692, function=0xda928a "gen_add2_insn") at /home/meissner/fsf-src/lra/gcc/diagnostic.c:1146
(gdb) where
#0 fancy_abort (file=0xda8850 "/home/meissner/fsf-src/lra/gcc/optabs.c", line=4692, function=0xda928a "gen_add2_insn") at /home/meissner/fsf-src/lra/gcc/diagnostic.c:1146
#1 0x00000000007fd200 in gen_add2_insn (x=0x7ffff141f600, y=0x7ffff1448528) at /home/meissner/fsf-src/lra/gcc/optabs.c:4692
#2 0x00000000007bad2d in lra_emit_add (x=0x7ffff141f600, y=0x7ffff1448528, z=0x7ffff1922dd0) at /home/meissner/fsf-src/lra/gcc/lra.c:314
#3 0x00000000007c7fc9 in process_address (nop=<value optimized out>, before=0x7fffffffc900, after=0x7fffffffc8f8) at /home/meissner/fsf-src/lra/gcc/lra-constraints.c:2414
#4 0x00000000007ca2ce in curr_insn_transform () at /home/meissner/fsf-src/lra/gcc/lra-constraints.c:2715
#5 0x00000000007cca75 in lra_constraints (first_p=<value optimized out>) at /home/meissner/fsf-src/lra/gcc/lra-constraints.c:3502
#6 0x00000000007bc37d in lra (f=<value optimized out>) at /home/meissner/fsf-src/lra/gcc/lra.c:2280
#7 0x0000000000787309 in do_reload () at /home/meissner/fsf-src/lra/gcc/ira.c:4624
#8 rest_of_handle_reload () at /home/meissner/fsf-src/lra/gcc/ira.c:4737
#9 0x000000000081409a in execute_one_pass (pass=0x13edaa0) at /home/meissner/fsf-src/lra/gcc/passes.c:2328
#10 0x0000000000814515 in execute_pass_list (pass=0x13edaa0) at /home/meissner/fsf-src/lra/gcc/passes.c:2386
#11 0x0000000000814527 in execute_pass_list (pass=0x13ee2e0) at /home/meissner/fsf-src/lra/gcc/passes.c:2387
#12 0x00000000005dc952 in expand_function (node=0x7ffff1729818) at /home/meissner/fsf-src/lra/gcc/cgraphunit.c:1641
#13 0x00000000005de4c1 in expand_all_functions () at /home/meissner/fsf-src/lra/gcc/cgraphunit.c:1745
#14 compile () at /home/meissner/fsf-src/lra/gcc/cgraphunit.c:2043
#15 0x00000000005deb7a in finalize_compilation_unit () at /home/meissner/fsf-src/lra/gcc/cgraphunit.c:2120
#16 0x00000000004c6643 in c_write_global_declarations () at /home/meissner/fsf-src/lra/gcc/c/c-decl.c:10120
#17 0x00000000008b739d in compile_file () at /home/meissner/fsf-src/lra/gcc/toplev.c:559
#18 0x00000000008b8568 in do_compile (argc=8, argv=0x7fffffffcd38) at /home/meissner/fsf-src/lra/gcc/toplev.c:1884
#19 toplev_main (argc=8, argv=0x7fffffffcd38) at /home/meissner/fsf-src/lra/gcc/toplev.c:1960
#20 0x0000003fdd21ecdd in __libc_start_main () from /lib64/libc.so.6
#21 0x00000000004a4d19 in _start ()
(gdb) up
#1 0x00000000007fd200 in gen_add2_insn (x=0x7ffff141f600, y=0x7ffff1448528) at /home/meissner/fsf-src/lra/gcc/optabs.c:4692
(gdb) print y
$1 = (rtx_def *) 0x7ffff1448528
(gdb) pr
(unspec:DI [
(symbol_ref:DI ("*.LANCHOR0") [flags 0x182])
(reg:DI 2 2)
] UNSPEC_TOCREL)
(gdb) up
#2 0x00000000007bad2d in lra_emit_add (x=0x7ffff141f600, y=0x7ffff1448528, z=0x7ffff1922dd0) at /home/meissner/fsf-src/lra/gcc/lra.c:314
(gdb) up
#3 0x00000000007c7fc9 in process_address (nop=<value optimized out>, before=0x7fffffffc900, after=0x7fffffffc8f8) at /home/meissner/fsf-src/lra/gcc/lra-constraints.c:2414
(gdb) print addr
$6 = (rtx_def *) 0x7ffff1448510
(gdb) pr
(plus:DI (unspec:DI [
(symbol_ref:DI ("*.LANCHOR0") [flags 0x182])
(reg:DI 2 2)
] UNSPEC_TOCREL)
(const_int 400 [0x190]))
(gdb) up
#4 0x00000000007ca2ce in curr_insn_transform () at /home/meissner/fsf-src/lra/gcc/lra-constraints.c:2715
(gdb) up
#5 0x00000000007cca75 in lra_constraints (first_p=<value optimized out>) at /home/meissner/fsf-src/lra/gcc/lra-constraints.c:3502
(gdb) print curr_insn
$9 = (rtx) 0x7ffff16d25e8
(gdb) pr
(insn 78 77 80 2 (set (mem/c:TI (plus:DI (unspec:DI [
(symbol_ref:DI ("*.LANCHOR0") [flags 0x182])
(reg:DI 2 2)
] UNSPEC_TOCREL)
(const_int 400 [0x190])) [5 sgftree+0 S16 A64])
(reg:TI 430 [ *tree_28(D) ])) interface/play_ascii.c:561 381 {*movti_ppc64}
(expr_list:REG_DEAD (reg:TI 430 [ *tree_28(D) ])
(nil)))
(gdb)
I am planning on trying to revamp movti's shortly. One of the things I put on
my do someday list back in the initial power7 days was allowing movti's in the
VSX registers.
Index: lra-constraints.c =================================================================== --- lra-constraints.c (revision 194263) +++ lra-constraints.c (working copy) @@ -685,7 +685,7 @@ match_reload (signed char out, signed ch new_out_reg = gen_lowpart_SUBREG (outmode, reg); else new_out_reg = gen_rtx_SUBREG (outmode, reg, 0); - SUBREG_MATCH_RELOAD_P (new_out_reg) = 1; + LRA_SUBREG_P (new_out_reg) = 1; /* If the input reg is dying here, we can use the same hard register for REG and IN_RTX. We do it only for original pseudos as reload pseudos can die although original @@ -709,7 +709,7 @@ match_reload (signed char out, signed ch it at the end of LRA work. */ clobber = emit_clobber (new_out_reg); LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1; - SUBREG_MATCH_RELOAD_P (new_in_reg) = 1; + LRA_SUBREG_P (new_in_reg) = 1; if (GET_CODE (in_rtx) == SUBREG) { rtx subreg_reg = SUBREG_REG (in_rtx); @@ -842,12 +842,15 @@ static rtx emit_spill_move (bool to_p, rtx mem_pseudo, rtx val) { if (GET_MODE (mem_pseudo) != GET_MODE (val)) - val = gen_rtx_SUBREG (GET_MODE (mem_pseudo), - GET_CODE (val) == SUBREG ? SUBREG_REG (val) : val, - 0); + { + val = gen_rtx_SUBREG (GET_MODE (mem_pseudo), + GET_CODE (val) == SUBREG ? SUBREG_REG (val) : val, + 0); + LRA_SUBREG_P (val) = 1; + } return (to_p - ? gen_move_insn (mem_pseudo, val) - : gen_move_insn (val, mem_pseudo)); + ? gen_move_insn (mem_pseudo, val) + : gen_move_insn (val, mem_pseudo)); } /* Process a special case insn (register move), return true if we @@ -1193,7 +1196,7 @@ simplify_operand_subreg (int nop, enum m SUBREG_BYTE (operand), mode) < 0 /* Don't reload subreg for matching reload. It is actually valid subreg in LRA. */ - && ! SUBREG_MATCH_RELOAD_P (operand)) + && ! LRA_SUBREG_P (operand)) || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg)) { enum op_type type = curr_static_id->operand[nop].type; Index: recog.c =================================================================== --- recog.c (revision 194263) +++ recog.c (working copy) @@ -1067,7 +1067,8 @@ register_operand (rtx op, enum machine_m && REGNO (sub) < FIRST_PSEUDO_REGISTER && REG_CANNOT_CHANGE_MODE_P (REGNO (sub), GET_MODE (sub), mode) && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_INT - && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_FLOAT) + && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_FLOAT + && ! LRA_SUBREG_P (op)) return 0; #endif Index: rtl.h =================================================================== --- rtl.h (revision 194263) +++ rtl.h (working copy) @@ -268,7 +268,7 @@ struct GTY((chain_next ("RTX_NEXT (&%h)" In a CODE_LABEL, part of the two-bit alternate entry field. 1 in a CONCAT is VAL_EXPR_IS_COPIED in var-tracking.c. 1 in a VALUE is SP_BASED_VALUE_P in cselib.c. - 1 in a SUBREG generated by LRA for matching reload. */ + 1 in a SUBREG generated by LRA for reload insns. */ unsigned int jump : 1; /* In a CODE_LABEL, part of the two-bit alternate entry field. 1 in a MEM if it cannot trap. @@ -1416,10 +1416,10 @@ do { \ ((RTL_FLAG_CHECK1("SUBREG_PROMOTED_UNSIGNED_P", (RTX), SUBREG)->volatil) \ ? -1 : (int) (RTX)->unchanging) -/* True if the subreg was generated by LRA for matching reload. Such +/* True if the subreg was generated by LRA for reload insns. Such subregs are valid only during LRA. */ -#define SUBREG_MATCH_RELOAD_P(RTX) \ - (RTL_FLAG_CHECK1("SUBREG_MATCH_RELOAD_P", (RTX), SUBREG)->jump) +#define LRA_SUBREG_P(RTX) \ + (RTL_FLAG_CHECK1("LRA_SUBREG_P", (RTX), SUBREG)->jump) /* Access various components of an ASM_OPERANDS rtx. */