From patchwork Thu Jul 21 15:33:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georg-Johann Lay X-Patchwork-Id: 651239 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rwHrB3CfCz9sxS for ; Fri, 22 Jul 2016 01:34:02 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=qN1h7DMS; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=ynunaNSB/Xe0RLu7S4UMHSIoOwnOyjQDlSsAlA8nDaqoNOtnYt ANv7DTvFwI13jdAs9pZEQcyyTw1t/uRn/vB5WnX9R9UxFCd8dRyVJXC6J+8qKzOv JD+W/IGIQkj7W4lc0M+4RGmFD6xyo93t128P0K4u03mvIbx6K5QRrPkqw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:message-id:date:mime-version:content-type; s= default; bh=ADv8HRBicEkph+KHFTewTCXZW3E=; b=qN1h7DMSB1PlieW/5ker 3ebTSdGXPdbUY6ZzMJOFgbGB4J9iQakDxsnfeKElw/qHc9PwHVpF/n1t8RTA++mK WT5gt+DhtUpQeIFNXXAKj8jBfAx1KgnOFvA+wMqKHtcmaRtgH4T/emdwNiJ46MtD lJdjsRF4uoI9a+DwAXcRVzs= Received: (qmail 1554 invoked by alias); 21 Jul 2016 15:33:45 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 1508 invoked by uid 89); 21 Jul 2016 15:33:44 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.1 required=5.0 tests=AWL, BAYES_50, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_LOW autolearn=no version=3.3.2 spammy=sk:avr_pri, sk:!addr_s, sk:ADDR_S, sk:!ADDR_S X-HELO: mo4-p00-ob.smtp.rzone.de Received: from mo4-p00-ob.smtp.rzone.de (HELO mo4-p00-ob.smtp.rzone.de) (81.169.146.220) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Thu, 21 Jul 2016 15:33:34 +0000 X-RZG-AUTH: :LXoWVUeid/7A29J/hMvvT3ol15ykJcYwR/bcHRirORRW3yMcVao= X-RZG-CLASS-ID: mo00 Received: from [192.168.0.123] (mail.hightec-rt.com [213.135.1.215]) by smtp.strato.de (RZmta 38.13 DYNA|AUTH) with ESMTPSA id 001eacs6LFXSNCn (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (curve secp521r1 with 521 ECDH bits, eq. 15360 bits RSA)) (Client did not present a certificate); Thu, 21 Jul 2016 17:33:28 +0200 (CEST) To: gcc-patches Cc: Denis Chertykov From: Georg-Johann Lay Subject: [patch,avr] remove secondary_reload hook implementation Message-ID: <4c35bdd2-8343-e417-0b92-8ead65634d79@gjlay.de> Date: Thu, 21 Jul 2016 17:33:28 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 X-IsSubscribed: yes This removes avr's TARGET_SECONDARY_RELOAD implementation which never worked as expected... Its intention was to provide an 8-bit scratch register for loads from non-generic address-spaces as they might need to set RAMPZ to the needed flash segment. The avr BE uses avr_find_unused_d_reg for that purpose, and if that function does not come up with a d-reg then the using function avr_out_lpm cooks up a scratch on the fly. Ok for trunk? Johann * config/avr/avr.c (TARGET_SECONDARY_RELOAD): Remove hook define... (avr_secondary_reload): ...and implementation. (avr_adjust_insn_length) [ADJUST_LEN_LPM]: Remove handling. * config/avr/avr.md (reload_in): Remove insns. (adjust_len) [lpm]: Remove insn attribute value. * config/avr/predicates.md (flash_operand): Remove insn predicate. Index: config/avr/avr.c =================================================================== --- config/avr/avr.c (revision 238587) +++ config/avr/avr.c (working copy) @@ -2048,50 +2048,6 @@ avr_legitimize_reload_address (rtx *px, } -/* Implement `TARGET_SECONDARY_RELOAD' */ - -static reg_class_t -avr_secondary_reload (bool in_p, rtx x, - reg_class_t reload_class ATTRIBUTE_UNUSED, - machine_mode mode, secondary_reload_info *sri) -{ - if (in_p - && MEM_P (x) - && !ADDR_SPACE_GENERIC_P (MEM_ADDR_SPACE (x)) - && ADDR_SPACE_MEMX != MEM_ADDR_SPACE (x)) - { - /* For the non-generic 16-bit spaces we need a d-class scratch. */ - - switch (mode) - { - default: - gcc_unreachable(); - - case QImode: sri->icode = CODE_FOR_reload_inqi; break; - case QQmode: sri->icode = CODE_FOR_reload_inqq; break; - case UQQmode: sri->icode = CODE_FOR_reload_inuqq; break; - - case HImode: sri->icode = CODE_FOR_reload_inhi; break; - case HQmode: sri->icode = CODE_FOR_reload_inhq; break; - case HAmode: sri->icode = CODE_FOR_reload_inha; break; - case UHQmode: sri->icode = CODE_FOR_reload_inuhq; break; - case UHAmode: sri->icode = CODE_FOR_reload_inuha; break; - - case PSImode: sri->icode = CODE_FOR_reload_inpsi; break; - - case SImode: sri->icode = CODE_FOR_reload_insi; break; - case SFmode: sri->icode = CODE_FOR_reload_insf; break; - case SQmode: sri->icode = CODE_FOR_reload_insq; break; - case SAmode: sri->icode = CODE_FOR_reload_insa; break; - case USQmode: sri->icode = CODE_FOR_reload_inusq; break; - case USAmode: sri->icode = CODE_FOR_reload_inusa; break; - } - } - - return NO_REGS; -} - - /* Helper function to print assembler resp. track instruction sequence lengths. Always return "". @@ -8847,7 +8803,6 @@ avr_adjust_insn_length (rtx_insn *insn, case ADJUST_LEN_MOV32: output_movsisf (insn, op, &len); break; case ADJUST_LEN_MOVMEM: avr_out_movmem (insn, op, &len); break; case ADJUST_LEN_XLOAD: avr_out_xload (insn, op, &len); break; - case ADJUST_LEN_LPM: avr_out_lpm (insn, op, &len); break; case ADJUST_LEN_SEXT: avr_out_sign_extend (insn, op, &len); break; case ADJUST_LEN_SFRACT: avr_out_fract (insn, op, true, &len); break; @@ -13888,9 +13843,6 @@ avr_fold_builtin (tree fndecl, int n_arg #undef TARGET_MODE_DEPENDENT_ADDRESS_P #define TARGET_MODE_DEPENDENT_ADDRESS_P avr_mode_dependent_address_p -#undef TARGET_SECONDARY_RELOAD -#define TARGET_SECONDARY_RELOAD avr_secondary_reload - #undef TARGET_PRINT_OPERAND #define TARGET_PRINT_OPERAND avr_print_operand #undef TARGET_PRINT_OPERAND_ADDRESS Index: config/avr/avr.md =================================================================== --- config/avr/avr.md (revision 238587) +++ config/avr/avr.md (working copy) @@ -151,7 +151,7 @@ (define_attr "adjust_len" tsthi, tstpsi, tstsi, compare, compare64, call, mov8, mov16, mov24, mov32, reload_in16, reload_in24, reload_in32, ufract, sfract, round, - xload, lpm, movmem, + xload, movmem, ashlqi, ashrqi, lshrqi, ashlhi, ashrhi, lshrhi, ashlsi, ashrsi, lshrsi, @@ -455,23 +455,6 @@ (define_split ;;======================================================================== ;; Move stuff around -;; Secondary input reload from non-generic 16-bit address spaces -(define_insn "reload_in" - [(set (match_operand:MOVMODE 0 "register_operand" "=r") - (match_operand:MOVMODE 1 "flash_operand" "m")) - (clobber (match_operand:QI 2 "d_register_operand" "=d"))] - ;; Fixme: The insn condition must not test the address space. - ;; Because the gen tools refuse to generate insns for address spaces - ;; and will generate insn-codes.h to look like: - ;; #define CODE_FOR_reload_inhi CODE_FOR_nothing - "reload_completed || reload_in_progress" - { - return avr_out_lpm (insn, operands, NULL); - } - [(set_attr "adjust_len" "lpm") - (set_attr "cc" "clobber")]) - - ;; "loadqi_libgcc" ;; "loadhi_libgcc" ;; "loadpsi_libgcc" Index: config/avr/predicates.md =================================================================== --- config/avr/predicates.md (revision 238586) +++ config/avr/predicates.md (working copy) @@ -76,13 +76,6 @@ (define_predicate "nox_general_operand" (not (match_test "avr_load_libgcc_p (op)")) (not (match_test "avr_mem_memx_p (op)")))) -;; Return 1 if OP is a memory operand in one of the __flash* address spaces -(define_predicate "flash_operand" - (and (match_operand 0 "memory_operand") - (match_test "Pmode == mode") - (ior (match_test "!MEM_P (op)") - (match_test "avr_mem_flash_p (op)")))) - ;; Return 1 if OP is the zero constant for MODE. (define_predicate "const0_operand" (and (match_code "const_int,const_fixed,const_double")