From patchwork Thu Jun 29 13:56:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 782300 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wz1S93yTNz9s3s for ; Thu, 29 Jun 2017 23:57:13 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="IrTvmUOU"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:references:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=r4BdwM+48jtIRMyli miU2LQ++4YNXWHpq7bhrhY1l6SrDdVUGE8FyvrUv2GByNkz17wVK2op5xT3XUWym jBGvxb9sVan0MSBIkkJmTael87ZCrf1Z1gMvM0UkyMD5YmYPtt0exRmOp5Ze1dk3 Fb9WrLp2kJh8l8KwKKXeTK5zQk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:references:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=RMxZ3QdhO1nrWqeXwWJVcrF ydGc=; b=IrTvmUOUFOHEL57l/m39+ca+D3v0wL0Tugn24pAjvbyNbmJz9zCY63f Q8zLIl2R6m7nd6satJFRJ8AvEwqx2BYjecBd7SWEwVDrrlFsBs0e8hXsXh5mFFqx puc/Qu0eKQeSh7Ic90Ro0VCjcTHtbWX4p+2Odrw3moKOyNpuyo2E= Received: (qmail 117675 invoked by alias); 29 Jun 2017 13:57:03 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 117648 invoked by uid 89); 29 Jun 2017 13:57:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, RCVD_IN_SORBS_SPAM, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 29 Jun 2017 13:56:59 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AD826344; Thu, 29 Jun 2017 06:56:58 -0700 (PDT) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EB46D3F557; Thu, 29 Jun 2017 06:56:57 -0700 (PDT) Subject: [PATCH 3/3, GCC/ARM] Add support for ARM Cortex-R52 processor From: Thomas Preudhomme To: Kyrill Tkachov , Ramana Radhakrishnan , Richard Earnshaw , "gcc-patches@gcc.gnu.org" References: <9ab04ae2-a65a-11cc-dfaf-1a20a8137e4e@foss.arm.com> Message-ID: <4a5c2985-ffab-3d06-ac02-acbbaf326869@foss.arm.com> Date: Thu, 29 Jun 2017 14:56:56 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 In-Reply-To: <9ab04ae2-a65a-11cc-dfaf-1a20a8137e4e@foss.arm.com> X-IsSubscribed: yes Hi, This patch adds support for the ARM Cortex-R52 processor rencently announced. [1] https://developer.arm.com/products/processors/cortex-r/cortex-r52 ChangeLog entry is as follows: *** gcc/ChangeLog *** 2017-01-31 Thomas Preud'homme * config/arm/arm-cpus.in (cortex-r52): Add new entry. * config/arm/arm-cpu.h: Regenerate. * config/arm/arm-cpu-cdata.h: Regenerate. * config/arm/arm-cpu-data.h: Regenerate. * config/arm/arm-tables.opt: Regenerate. * config/arm/bpabi.h (BE8_LINK_SPEC): Add entry for ARM Cortex-R52. * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM Cortex-R52. * doc/invoke.texi: Mention -mtune=cortex-r52. Tested by building an arm-none-eabi GCC cross-compiler targeting Cortex-R52. Is this ok for stage1? Best regards, Thomas diff --git a/gcc/config/arm/arm-cpu-cdata.h b/gcc/config/arm/arm-cpu-cdata.h index 0a122f5febaaceeeb5a405cb5a64e1edd9b044f3..043b5b2db09146b5686a5fe602f907164f9d84c5 100644 --- a/gcc/config/arm/arm-cpu-cdata.h +++ b/gcc/config/arm/arm-cpu-cdata.h @@ -803,6 +803,13 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = }, }, { + "cortex-r52", + { + ISA_ARMv8r,isa_bit_crc32, + isa_nobit + }, + }, + { "armv2", { ISA_ARMv2,isa_bit_mode26, diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h index 48c1d88032c1c5dc7c6cba71511f79fe9f2533ea..0677132382fad2f1baf1fbdf5c0b03fe32f752e2 100644 --- a/gcc/config/arm/arm-cpu-data.h +++ b/gcc/config/arm/arm-cpu-data.h @@ -1132,6 +1132,16 @@ static const struct processors all_cores[] = }, &arm_v7m_tune }, + { + "cortex-r52", TARGET_CPU_cortexr52, + (TF_LDSCHED), + "8R", BASE_ARCH_8R, + { + ISA_ARMv8r,isa_bit_crc32, + isa_nobit + }, + &arm_cortex_tune + }, {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL} }; diff --git a/gcc/config/arm/arm-cpu.h b/gcc/config/arm/arm-cpu.h index cd282db02f56f4416ff82eb3d8d569cd99fb0d41..4d6ea61d07dc98540f0f75679d8ef6f7eafc10bb 100644 --- a/gcc/config/arm/arm-cpu.h +++ b/gcc/config/arm/arm-cpu.h @@ -132,6 +132,7 @@ enum processor_type TARGET_CPU_cortexa73cortexa53, TARGET_CPU_cortexm23, TARGET_CPU_cortexm33, + TARGET_CPU_cortexr52, TARGET_CPU_arm_none }; diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index be1f0ca4e38ae76683b77d8c3b79a066e62325d7..139aa561d3f918655978e44b5bcb6c0b50747a08 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -1104,6 +1104,16 @@ begin cpu cortex-m33 costs v7m end cpu cortex-m33 + +# V8 R-profile implementations. +begin cpu cortex-r52 + cname cortexr52 + tune flags LDSCHED + architecture armv8-r+crc + costs cortex +end cpu cortex-r52 + + # FPU entries # format: # begin fpu diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index 7bab5de5a39e9192c97851929b83175648158cdf..ccd1a7661fb97938ddea7670eebe1a0f48efb929 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -354,6 +354,9 @@ Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23) EnumValue Enum(processor_type) String(cortex-m33) Value( TARGET_CPU_cortexm33) +EnumValue +Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52) + Enum Name(arm_arch) Type(int) Known ARM architectures (for use with the -march= option): diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h index c394ac805c7577113ed72b31a06ff93dc7f5f490..c3dca1cd4833afd67e56a276ef0e9c1e17f4fae4 100644 --- a/gcc/config/arm/bpabi.h +++ b/gcc/config/arm/bpabi.h @@ -100,7 +100,7 @@ |march=armv8-m.main \ |march=armv8-m.main+dsp|mcpu=cortex-m33 \ |march-armv8-r \ - |march-armv8-r+crc \ + |march-armv8-r+crc|mcpu=cortex-r52 \ :%{!r:--be8}}}" #else #define BE8_LINK_SPEC \ @@ -142,7 +142,7 @@ |march=armv8-m.main \ |march=armv8-m.main+dsp|mcpu=cortex-m33 \ |march=armv8-r \ - |march=armv8-r+crc \ + |march=armv8-r+crc|mcpu=cortex-r52 \ :%{!r:--be8}}}" #endif diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c index 29873d57a1e45fd989f6ff01dd4a2ae7320d93bb..00f8128e6911a79f83da03bf731c1cc9127c7285 100644 --- a/gcc/config/arm/driver-arm.c +++ b/gcc/config/arm/driver-arm.c @@ -56,6 +56,7 @@ static struct vendor_cpu arm_cpu_table[] = { {"0xc15", "armv7-r", "cortex-r5"}, {"0xc17", "armv7-r", "cortex-r7"}, {"0xc18", "armv7-r", "cortex-r8"}, + {"0xd13", "armv8-r+crc", "cortex-r52"}, {"0xc20", "armv6-m", "cortex-m0"}, {"0xc21", "armv6-m", "cortex-m1"}, {"0xc23", "armv7-m", "cortex-m3"}, diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 9ea580626749dc9d27bb72d56bbbef6a474a5055..a871837426485dd6a87c541386964bf85dfafde7 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -15212,6 +15212,7 @@ Permissible names are: @samp{arm2}, @samp{arm250}, @samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, +@samp{cortex-r52}, @samp{cortex-m33}, @samp{cortex-m23}, @samp{cortex-m7},