From patchwork Mon Oct 24 13:30:44 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Huber X-Patchwork-Id: 121352 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 8D070B6F84 for ; Tue, 25 Oct 2011 00:31:09 +1100 (EST) Received: (qmail 4633 invoked by alias); 24 Oct 2011 13:31:06 -0000 Received: (qmail 4624 invoked by uid 22791); 24 Oct 2011 13:31:05 -0000 X-SWARE-Spam-Status: No, hits=-0.5 required=5.0 tests=AWL, BAYES_00, RDNS_DYNAMIC, T_FILL_THIS_FORM_SHORT X-Spam-Check-By: sourceware.org Received: from host-82-135-62-35.customer.m-online.net (HELO mail.embedded-brains.de) (82.135.62.35) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 24 Oct 2011 13:30:47 +0000 Received: by mail.embedded-brains.de (Postfix, from userid 65534) id 5B7276525B0; Mon, 24 Oct 2011 15:30:44 +0200 (CEST) Received: from [192.168.96.31] (eb0011.eb.z [192.168.96.31]) by mail.embedded-brains.de (Postfix) with ESMTP id 3083B6525AE; Mon, 24 Oct 2011 15:30:44 +0200 (CEST) Message-ID: <4EA56884.4020703@embedded-brains.de> Date: Mon, 24 Oct 2011 15:30:44 +0200 From: Sebastian Huber User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.23) Gecko/20110920 SUSE/3.1.15 Lightning/1.0b2 Thunderbird/3.1.15 MIME-Version: 1.0 To: Richard Earnshaw CC: Bernd Schmidt , GCC Patches , Ramana Radhakrishnan Subject: Re: [ARM] Fix PR49641 References: <4E1610ED.2070108@codesourcery.com> <4E1DA5C4.60806@arm.com> <4E983996.4030908@codesourcery.com> <4E9C2586.7080804@arm.com> <4E9D6EC0.10908@codesourcery.com> <4E9D7155.7050905@arm.com> <4E9D754A.4040804@codesourcery.com> <4E9D79F7.8030407@arm.com> In-Reply-To: <4E9D79F7.8030407@arm.com> X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hello, what about the attached patch based on the original patch provided by Bernd Schmidt with modifications suggested by Richard Earnshaw. * config/arm/arm.c (store_multiple_sequence): Avoid cases where the base reg is stored iff compiling for Thumb1. * gcc.target/arm/pr49641.c: New test. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index fcdb8a1..63b5a8b 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -9812,6 +9812,9 @@ store_multiple_sequence (rtx *operands, int nops, int nops_total, rtx base_reg_rtx = NULL; int i, stm_case; + /* Write back of base register is currently only supported for Thumb 1. */ + int base_writeback = TARGET_THUMB1; + /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be easily extended if required. */ gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS); @@ -9869,7 +9872,9 @@ store_multiple_sequence (rtx *operands, int nops, int nops_total, /* If it isn't an integer register, then we can't do this. */ if (unsorted_regs[i] < 0 || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM) - || (TARGET_THUMB2 && unsorted_regs[i] == base_reg) + /* The effects are unpredictable if the base register is + both updated and stored. */ + || (base_writeback && unsorted_regs[i] == base_reg) || (TARGET_THUMB2 && unsorted_regs[i] == SP_REGNUM) || unsorted_regs[i] > 14) return 0; diff --git a/gcc/testsuite/gcc.target/arm/pr49641.c b/gcc/testsuite/gcc.target/arm/pr49641.c new file mode 100644 index 0000000..7f9b376 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr49641.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-final { scan-assembler-not "stmia\[\\t \]*r3!\[^\\n]*r3" } } */ +typedef struct { + void *t1, *t2, *t3; +} z; +extern volatile int y; +static inline void foo(z *x) { + x->t1 = &x->t2; + x->t2 = ((void *)0); + x->t3 = &x->t1; +} +extern z v; +void bar (void) { + y = 0; + foo(&v); +}