From patchwork Fri Oct 21 17:50:06 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aldy Hernandez X-Patchwork-Id: 121037 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id A71DAB70B2 for ; Sat, 22 Oct 2011 04:50:31 +1100 (EST) Received: (qmail 15940 invoked by alias); 21 Oct 2011 17:50:29 -0000 Received: (qmail 15928 invoked by uid 22791); 21 Oct 2011 17:50:28 -0000 X-SWARE-Spam-Status: No, hits=-6.7 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, SPF_HELO_PASS X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 21 Oct 2011 17:50:11 +0000 Received: from int-mx02.intmail.prod.int.phx2.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p9LHo7Xi007712 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 21 Oct 2011 13:50:07 -0400 Received: from houston.quesejoda.com (vpn-238-179.phx2.redhat.com [10.3.238.179]) by int-mx02.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id p9LHo69d026242; Fri, 21 Oct 2011 13:50:06 -0400 Message-ID: <4EA1B0CE.3030208@redhat.com> Date: Fri, 21 Oct 2011 12:50:06 -0500 From: Aldy Hernandez User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:7.0) Gecko/20110927 Thunderbird/7.0 MIME-Version: 1.0 To: Andrew MacLeod CC: "H.J. Lu" , "Joseph S. Myers" , gcc-patches Subject: Re: [cxx-mem-model] Handle x86-64 with -m32 References: <4EA08C57.7030204@redhat.com> <4EA1616E.2050601@redhat.com> <4EA1990A.70904@redhat.com> In-Reply-To: <4EA1990A.70904@redhat.com> Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On 10/21/11 11:08, Andrew MacLeod wrote: > On 10/21/2011 11:28 AM, H.J. Lu wrote: >> On Fri, Oct 21, 2011 at 5:11 AM, Andrew MacLeod >> wrote: >>>> >>>> X32 has native int64 and int128. >>>> >>> I presume there is no atomic support for int128 though, and thats what >>> 'condition check_effective_target_sync_int_128' is testing for. >>> >> X32 uses x86-64 instruction set with 32bit pointers. It has the same >> atomic support as x86-64 and has atomic support for int128. > > Oh, you aren't talking about 32 bit, but a 32 bit abi on a 64 bit machine. Thanks for pointing this out Joseph. The following patch handles both x86_64 and i?86, but only returns true for LP64. Is this what you had in mind? Aldy * lib/target-supports.exp (check_effective_target_sync_int_128): Handle both 32-bit and 64-bit triplets on x86. (check_effective_target_sync_long_long): Same. * gcc.dg/simulate-thread/atomic-load-int128.c: Handle i?86-*-*. * gcc.dg/simulate-thread/atomic-other-int128.c: Same. Index: lib/target-supports.exp =================================================================== --- lib/target-supports.exp (revision 180156) +++ lib/target-supports.exp (working copy) @@ -3456,7 +3456,8 @@ proc check_effective_target_sync_int_128 verbose "check_effective_target_sync_int_128: using cached result" 2 } else { set et_sync_int_128_saved 0 - if { [istarget x86_64-*-*] } { + if { ([istarget x86_64-*-*] || [istarget i?86-*-*]) + && [is-effective-target lp64] } { set et_sync_int_128_saved 1 } } @@ -3474,7 +3475,8 @@ proc check_effective_target_sync_long_lo verbose "check_effective_target_sync_long_long: using cached result" 2 } else { set et_sync_long_long_saved 0 - if { [istarget x86_64-*-*] } { + if { ([istarget x86_64-*-*] || [istarget i?86-*-*]) + && [is-effective-target lp64] } { set et_sync_long_long_saved 1 } } Index: gcc.dg/simulate-thread/atomic-load-int128.c =================================================================== --- gcc.dg/simulate-thread/atomic-load-int128.c (revision 180156) +++ gcc.dg/simulate-thread/atomic-load-int128.c (working copy) @@ -1,6 +1,6 @@ /* { dg-do link } */ /* { dg-require-effective-target sync_int_128 } */ -/* { dg-options "-mcx16" { target { x86_64-*-* } } } */ +/* { dg-options "-mcx16" { target { x86_64-*-* i?86-*-* } } } */ /* { dg-final { simulate-thread } } */ #include Index: gcc.dg/simulate-thread/atomic-other-int128.c =================================================================== --- gcc.dg/simulate-thread/atomic-other-int128.c (revision 180156) +++ gcc.dg/simulate-thread/atomic-other-int128.c (working copy) @@ -1,6 +1,6 @@ /* { dg-do link } */ /* { dg-require-effective-target sync_int_128 } */ -/* { dg-options "-mcx16" { target { x86_64-*-* } } } */ +/* { dg-options "-mcx16" { target { x86_64-*-* i?86-*-*] } } } */ /* { dg-final { simulate-thread } } */ #include