Index: ira.c
===================================================================
--- ira.c	(revision 173706)
+++ ira.c	(working copy)
@@ -799,27 +799,30 @@ setup_pressure_classes (void)
     {
       if (ira_available_class_regs[cl] == 0)
 	continue;
-      /* Check that the moves between any hard registers of the
-	 current class are not more expensive for a legal mode than
-	 load/store of the hard registers of the current class.  Such
-	 class is a potential candidate to be a register pressure
-	 class.  */
-      for (m = 0; m < NUM_MACHINE_MODES; m++)
+      if (ira_available_class_regs[cl] != 1)
 	{
-	  COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
-	  AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
-	  AND_COMPL_HARD_REG_SET (temp_hard_regset,
-				  ira_prohibited_class_mode_regs[cl][m]);
-	  if (hard_reg_set_empty_p (temp_hard_regset))
+	  /* Check that the moves between any hard registers of the
+	     current class are not more expensive for a legal mode
+	     than load/store of the hard registers of the current
+	     class.  Such class is a potential candidate to be a
+	     register pressure class.  */
+	  for (m = 0; m < NUM_MACHINE_MODES; m++)
+	    {
+	      COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
+	      AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+	      AND_COMPL_HARD_REG_SET (temp_hard_regset,
+				      ira_prohibited_class_mode_regs[cl][m]);
+	      if (hard_reg_set_empty_p (temp_hard_regset))
+		continue;
+	      ira_init_register_move_cost_if_necessary ((enum machine_mode) m);
+	      cost = ira_register_move_cost[m][cl][cl];
+	      if (cost <= ira_max_memory_move_cost[m][cl][1]
+		  || cost <= ira_max_memory_move_cost[m][cl][0])
+		break;
+	    }
+	  if (m >= NUM_MACHINE_MODES)
 	    continue;
-	  ira_init_register_move_cost_if_necessary ((enum machine_mode) m);
-	  cost = ira_register_move_cost[m][cl][cl];
-	  if (cost <= ira_max_memory_move_cost[m][cl][1]
-	      || cost <= ira_max_memory_move_cost[m][cl][0])
-	    break;
 	}
-      if (m >= NUM_MACHINE_MODES)
-	continue;
       curr = 0;
       insert_p = true;
       COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
@@ -848,6 +851,8 @@ setup_pressure_classes (void)
 	      && (! hard_reg_set_equal_p (temp_hard_regset2, temp_hard_regset)
 		  || cl == (int) GENERAL_REGS))
 	    continue;
+	  if (hard_reg_set_equal_p (temp_hard_regset2, temp_hard_regset))
+	    insert_p = false;
 	  pressure_classes[curr++] = (enum reg_class) cl2;
 	}
       /* If the current candidate is a subset of a so far added
@@ -858,23 +863,44 @@ setup_pressure_classes (void)
       n = curr;
     }
 #ifdef ENABLE_IRA_CHECKING
-  /* Check pressure classes correctness: here we check that hard
-     registers from all register pressure classes contains all hard
-     registers available for the allocation.  */
-  CLEAR_HARD_REG_SET (temp_hard_regset);
-  CLEAR_HARD_REG_SET (temp_hard_regset2);
-  for (cl = 0; cl < LIM_REG_CLASSES; cl++)
-    {
-      for (i = 0; i < n; i++)
-	if ((int) pressure_classes[i] == cl)
-	  break;
-      IOR_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]);
-      if (i >= n)
-	IOR_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
-    }
-  AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
-  AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
-  ira_assert (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset));
+  {
+    HARD_REG_SET ignore_hard_regs;
+
+    /* Check pressure classes correctness: here we check that hard
+       registers from all register pressure classes contains all hard
+       registers available for the allocation.  */
+    CLEAR_HARD_REG_SET (temp_hard_regset);
+    CLEAR_HARD_REG_SET (temp_hard_regset2);
+    COPY_HARD_REG_SET (ignore_hard_regs, no_unit_alloc_regs);
+    for (cl = 0; cl < LIM_REG_CLASSES; cl++)
+      {
+	/* For some targets (like MIPS with MD_REGS), there are some
+	   classes with hard registers available for allocation but
+	   not able to hold value of any mode.  */
+	for (m = 0; m < NUM_MACHINE_MODES; m++)
+	  if (contains_reg_of_mode[cl][m])
+	    break;
+	if (m >= NUM_MACHINE_MODES)
+	  {
+	    IOR_HARD_REG_SET (ignore_hard_regs, reg_class_contents[cl]);
+	    continue;
+	  }
+	for (i = 0; i < n; i++)
+	  if ((int) pressure_classes[i] == cl)
+	    break;
+	IOR_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]);
+	if (i < n)
+	  IOR_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
+      }
+    for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+      /* Some targets (like SPARC with ICC reg) have alocatable regs
+	 for which no reg class is defined.  */
+      if (REGNO_REG_CLASS (i) == NO_REGS)
+	SET_HARD_REG_BIT (ignore_hard_regs, i);
+    AND_COMPL_HARD_REG_SET (temp_hard_regset, ignore_hard_regs);
+    AND_COMPL_HARD_REG_SET (temp_hard_regset2, ignore_hard_regs);
+    ira_assert (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset));
+  }
 #endif
   ira_pressure_classes_num = 0;
   for (i = 0; i < n; i++)
