From patchwork Fri Mar 25 00:12:04 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 88291 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 1C933B6FAC for ; Fri, 25 Mar 2011 11:12:22 +1100 (EST) Received: (qmail 18009 invoked by alias); 25 Mar 2011 00:12:18 -0000 Received: (qmail 17991 invoked by uid 22791); 25 Mar 2011 00:12:14 -0000 X-SWARE-Spam-Status: No, hits=-6.1 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_HI, SPF_HELO_PASS, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 25 Mar 2011 00:12:05 +0000 Received: from int-mx02.intmail.prod.int.phx2.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p2P0C5Z9014470 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Thu, 24 Mar 2011 20:12:05 -0400 Received: from anchor.twiddle.home (ovpn-113-104.phx2.redhat.com [10.3.113.104]) by int-mx02.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id p2P0C4VQ014990 for ; Thu, 24 Mar 2011 20:12:05 -0400 Message-ID: <4D8BDDD4.5060203@redhat.com> Date: Thu, 24 Mar 2011 17:12:04 -0700 From: Richard Henderson User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.15) Gecko/20110307 Fedora/3.1.9-0.39.b3pre.fc14 Thunderbird/3.1.9 MIME-Version: 1.0 To: GCC Patches Subject: [alpha] Unify zero_extend patterns with attribute enabled X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org The attribute enabled feature can help avoid quite a lot of duplication in the alpha backend. This begins the process by tackling the easiest -- zero_extension, conditionalized on the existance of the BWX instruction set extension. Tested on alpha{,ev5,ev56,ev67}-linux. r~ + * config/alpha/alpha.md (attribute isa): New. + (attribute enabled): New. + (zero_extendqihi2): Merge from *zero_extendqihi2_{bwx,nobwx}. + (zero_extendqisi2, zero_extendqidi2): Similarly. + (zero_extendhisi2, zero_extendhidi2): Similarly. + * config/alpha/predicates.md (reg_or_bwx_memory_operand): New. + diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 38d40b5..cb3821c 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -177,6 +177,18 @@ (define_attr "cannot_copy" "false,true" (const_string "false")) + +;; Used to control the "enabled" attribute on a per-instruction basis. +(define_attr "isa" "base,bwx,max,fix,cix" + (const_string "base")) + +(define_attr "enabled" "" + (cond [(eq_attr "isa" "bwx") (symbol_ref "TARGET_BWX") + (eq_attr "isa" "max") (symbol_ref "TARGET_MAX") + (eq_attr "isa" "fix") (symbol_ref "TARGET_FIX") + (eq_attr "isa" "cix") (symbol_ref "TARGET_CIX") + ] + (const_int 1))) ;; Include scheduling descriptions. @@ -1092,130 +1104,60 @@ operands[4] = GEN_INT (mask2); }) -(define_expand "zero_extendqihi2" - [(set (match_operand:HI 0 "register_operand" "") - (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))] - "" -{ - if (! TARGET_BWX) - operands[1] = force_reg (QImode, operands[1]); -}) - -(define_insn "*zero_extendqihi2_bwx" +(define_insn "zero_extendqihi2" [(set (match_operand:HI 0 "register_operand" "=r,r") - (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] - "TARGET_BWX" + (zero_extend:HI + (match_operand:QI 1 "reg_or_bwx_memory_operand" "r,m")))] + "" "@ and %1,0xff,%0 ldbu %0,%1" - [(set_attr "type" "ilog,ild")]) + [(set_attr "type" "ilog,ild") + (set_attr "isa" "*,bwx")]) -(define_insn "*zero_extendqihi2_nobwx" - [(set (match_operand:HI 0 "register_operand" "=r") - (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))] - "! TARGET_BWX" - "and %1,0xff,%0" - [(set_attr "type" "ilog")]) - -(define_expand "zero_extendqisi2" - [(set (match_operand:SI 0 "register_operand" "") - (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] - "" -{ - if (! TARGET_BWX) - operands[1] = force_reg (QImode, operands[1]); -}) - -(define_insn "*zero_extendqisi2_bwx" +(define_insn "zero_extendqisi2" [(set (match_operand:SI 0 "register_operand" "=r,r") - (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] - "TARGET_BWX" + (zero_extend:SI + (match_operand:QI 1 "reg_or_bwx_memory_operand" "r,m")))] + "" "@ and %1,0xff,%0 ldbu %0,%1" - [(set_attr "type" "ilog,ild")]) - -(define_insn "*zero_extendqisi2_nobwx" - [(set (match_operand:SI 0 "register_operand" "=r") - (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))] - "! TARGET_BWX" - "and %1,0xff,%0" - [(set_attr "type" "ilog")]) - -(define_expand "zero_extendqidi2" - [(set (match_operand:DI 0 "register_operand" "") - (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))] - "" -{ - if (! TARGET_BWX) - operands[1] = force_reg (QImode, operands[1]); -}) + [(set_attr "type" "ilog,ild") + (set_attr "isa" "*,bwx")]) -(define_insn "*zero_extendqidi2_bwx" +(define_insn "zero_extendqidi2" [(set (match_operand:DI 0 "register_operand" "=r,r") - (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] - "TARGET_BWX" + (zero_extend:DI + (match_operand:QI 1 "reg_or_bwx_memory_operand" "r,m")))] + "" "@ and %1,0xff,%0 ldbu %0,%1" - [(set_attr "type" "ilog,ild")]) - -(define_insn "*zero_extendqidi2_nobwx" - [(set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))] - "! TARGET_BWX" - "and %1,0xff,%0" - [(set_attr "type" "ilog")]) - -(define_expand "zero_extendhisi2" - [(set (match_operand:SI 0 "register_operand" "") - (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] - "" -{ - if (! TARGET_BWX) - operands[1] = force_reg (HImode, operands[1]); -}) + [(set_attr "type" "ilog,ild") + (set_attr "isa" "*,bwx")]) -(define_insn "*zero_extendhisi2_bwx" +(define_insn "zero_extendhisi2" [(set (match_operand:SI 0 "register_operand" "=r,r") - (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] - "TARGET_BWX" + (zero_extend:SI + (match_operand:HI 1 "reg_or_bwx_memory_operand" "r,m")))] + "" "@ zapnot %1,3,%0 ldwu %0,%1" - [(set_attr "type" "shift,ild")]) - -(define_insn "*zero_extendhisi2_nobwx" - [(set (match_operand:SI 0 "register_operand" "=r") - (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))] - "! TARGET_BWX" - "zapnot %1,3,%0" - [(set_attr "type" "shift")]) - -(define_expand "zero_extendhidi2" - [(set (match_operand:DI 0 "register_operand" "") - (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))] - "" -{ - if (! TARGET_BWX) - operands[1] = force_reg (HImode, operands[1]); -}) + [(set_attr "type" "shift,ild") + (set_attr "isa" "*,bwx")]) -(define_insn "*zero_extendhidi2_bwx" +(define_insn "zero_extendhidi2" [(set (match_operand:DI 0 "register_operand" "=r,r") - (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] - "TARGET_BWX" + (zero_extend:DI + (match_operand:HI 1 "reg_or_bwx_memory_operand" "r,m")))] + "" "@ zapnot %1,3,%0 ldwu %0,%1" - [(set_attr "type" "shift,ild")]) - -(define_insn "*zero_extendhidi2_nobwx" - [(set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))] - "" - "zapnot %1,3,%0" - [(set_attr "type" "shift")]) + [(set_attr "type" "shift,ild") + (set_attr "isa" "*,bwx")]) (define_insn "zero_extendsidi2" [(set (match_operand:DI 0 "register_operand" "=r") diff --git a/gcc/config/alpha/predicates.md b/gcc/config/alpha/predicates.md index da76d4f..e43564d 100644 --- a/gcc/config/alpha/predicates.md +++ b/gcc/config/alpha/predicates.md @@ -617,3 +617,9 @@ return false; return for_each_rtx (&op, some_small_symbolic_operand_int, NULL); }) + +;; Accept a register, or a memory if BWX is enabled. +(define_predicate "reg_or_bwx_memory_operand" + (ior (match_operand 0 "register_operand") + (and (match_test "TARGET_BWX") + (match_operand 0 "memory_operand"))))