From patchwork Tue Oct 19 19:16:10 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxim Kuvyrkov X-Patchwork-Id: 68374 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id CFB93B70CB for ; Wed, 20 Oct 2010 06:16:31 +1100 (EST) Received: (qmail 6608 invoked by alias); 19 Oct 2010 19:16:26 -0000 Received: (qmail 6593 invoked by uid 22791); 19 Oct 2010 19:16:22 -0000 X-SWARE-Spam-Status: No, hits=-1.9 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 19 Oct 2010 19:16:15 +0000 Received: (qmail 20823 invoked from network); 19 Oct 2010 19:16:13 -0000 Received: from unknown (HELO mbp.local) (maxim@127.0.0.2) by mail.codesourcery.com with ESMTPA; 19 Oct 2010 19:16:13 -0000 Message-ID: <4CBDEE7A.9020001@codesourcery.com> Date: Tue, 19 Oct 2010 23:16:10 +0400 From: Maxim Kuvyrkov User-Agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.6; en-US; rv:1.9.2.9) Gecko/20100915 Thunderbird/3.1.4 MIME-Version: 1.0 To: Richard Henderson CC: gcc-patches , Bernd Schmidt , "H.J. Lu" Subject: Re: 0002-Fix-32-bit-alignment for Core i7 References: <4CBD7F43.3050209@codesourcery.com> <4CBD8680.5010302@codesourcery.com> <4CBDD39A.6050609@redhat.com> In-Reply-To: <4CBDD39A.6050609@redhat.com> X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On 10/19/10 9:21 PM, Richard Henderson wrote: >> + PROCESSOR_COREI7_32, >> + PROCESSOR_COREI7_64, > > You had different tunings for 32 and 64-bit to come, right? > You've done it this way instead of > > TARGET_COREI7&& TARGET_32BIT > > because of the indicies into processor_target_table? Yes, that is one of the reasons. The other reason is tuning settings in initial_ix86_tune_features. The later may not be very clear because of ... > >> -#define m_GENERIC32 (1<> -#define m_GENERIC64 (1<> +#define m_GENERIC32 (1<> +#define m_GENERIC64 (1< > This bit I don't understand. Why does GENERIC include COREI7? ... this. This change [temporarily] aliases PROCESSOR_COREI7_* to PROCESSOR_GENERIC. One could have added m_COREI7_* to all the entries that mention m_GENERIC* instead, but it would not be as clear about the intent of the patch. In any case, the above hunk will be reverted by subsequent patches that will adjust initial_ix86_tune_features and related arrays. I missed hunks to ix86_option_override_internal() in the patch I posted, without it the rest of the patch would be a no-op. Attached is the full version. Regards, diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index 1846efb..3b4409e 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -122,6 +122,11 @@ ix86_target_macros_internal (int isa_flag, def_or_undef (parse_in, "__core2"); def_or_undef (parse_in, "__core2__"); break; + case PROCESSOR_COREI7_32: + case PROCESSOR_COREI7_64: + def_or_undef (parse_in, "__corei7"); + def_or_undef (parse_in, "__corei7__"); + break; case PROCESSOR_ATOM: def_or_undef (parse_in, "__atom"); def_or_undef (parse_in, "__atom__"); @@ -197,6 +202,10 @@ ix86_target_macros_internal (int isa_flag, case PROCESSOR_CORE2: def_or_undef (parse_in, "__tune_core2__"); break; + case PROCESSOR_COREI7_32: + case PROCESSOR_COREI7_64: + def_or_undef (parse_in, "__tune_corei7__"); + break; case PROCESSOR_ATOM: def_or_undef (parse_in, "__tune_atom__"); break; diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 71e0242..3bee0b7 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1355,6 +1355,8 @@ const struct processor_costs *ix86_cost = &pentium_cost; #define m_PENT4 (1<