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Wed, 07 Jul 2021 09:03:13 +0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 16793BTF29294982 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 7 Jul 2021 09:03:11 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A97514C063; Wed, 7 Jul 2021 09:03:11 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6862D4C04E; Wed, 7 Jul 2021 09:03:10 +0000 (GMT) Received: from kewenlins-mbp.cn.ibm.com (unknown [9.200.147.34]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 7 Jul 2021 09:03:10 +0000 (GMT) To: GCC Patches Subject: [PATCH] test/rs6000: Add case to cover vector division Message-ID: <46f73cc8-c323-656a-eb9e-49dd91b5ce76@linux.ibm.com> Date: Wed, 7 Jul 2021 17:03:07 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-GUID: XJ18TBG38sxGnJ4hsVYL4Xc1e1lQZKIP X-Proofpoint-ORIG-GUID: zepELficMTyan93IG2yg8R-k1_guutBe X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-07_05:2021-07-06, 2021-07-07 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 clxscore=1015 mlxlogscore=999 phishscore=0 priorityscore=1501 spamscore=0 malwarescore=0 adultscore=0 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2107070052 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Kewen.Lin via Gcc-patches" From: "Kewen.Lin" Reply-To: "Kewen.Lin" Cc: Bill Schmidt , David Edelsohn , Segher Boessenkool Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi, This patch is to add one test case to check if vectorizer can exploit vector division instrutions newly introduced by Power10. Is it ok for trunk? BR, Kewen ----- gcc/testsuite/ChangeLog: * gcc.target/powerpc/div-vectorize-1.c: New test. --- .../gcc.target/powerpc/div-vectorize-1.c | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/div-vectorize-1.c diff --git a/gcc/testsuite/gcc.target/powerpc/div-vectorize-1.c b/gcc/testsuite/gcc.target/powerpc/div-vectorize-1.c new file mode 100644 index 00000000000..6208b2dc1f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/div-vectorize-1.c @@ -0,0 +1,46 @@ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fdump-tree-vect-details" } */ + +/* Test vectorizer can exploit ISA 3.1 instructions Vector Divide + Signed/Unsigned Word/Doubleword for word/doubleword division. */ + +#define N 128 + +extern signed int si_a[N], si_b[N], si_c[N]; +extern unsigned int ui_a[N], ui_b[N], ui_c[N]; +extern signed long long sd_a[N], sd_b[N], sd_c[N]; +extern unsigned long long ud_a[N], ud_b[N], ud_c[N]; + +__attribute__ ((noipa)) void +test_si () +{ + for (int i = 0; i < N; i++) + si_c[i] = si_a[i] / si_b[i]; +} + +__attribute__ ((noipa)) void +test_ui () +{ + for (int i = 0; i < N; i++) + ui_c[i] = ui_a[i] / ui_b[i]; +} + +__attribute__ ((noipa)) void +test_sd () +{ + for (int i = 0; i < N; i++) + sd_c[i] = sd_a[i] / sd_b[i]; +} + +__attribute__ ((noipa)) void +test_ud () +{ + for (int i = 0; i < N; i++) + ud_c[i] = ud_a[i] / ud_b[i]; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ +/* { dg-final { scan-assembler-times {\mvdivsw\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvdivuw\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvdivsd\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvdivud\M} 1 } } */