[v3] RISC-V: Add autovec FP unary operations.

Message ID	4288ccbd-68dd-a58d-c068-e352111f21bc@gmail.com
State	New
Headers	show Return-Path: <gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org> DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3FA643858D35 Message-ID: <4288ccbd-68dd-a58d-c068-e352111f21bc@gmail.com> Date: Fri, 16 Jun 2023 15:32:09 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Cc: rdapp.gcc@gmail.com Subject: [PATCH v3] RISC-V: Add autovec FP unary operations. Content-Language: en-US To: gcc-patches <gcc-patches@gcc.gnu.org>, palmer <palmer@dabbelt.com>, Kito Cheng <kito.cheng@gmail.com>, "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>, jeffreyalaw <jeffreyalaw@gmail.com> References: <490fd4af-75d2-de76-fa74-f9ebb478b8b8@gmail.com> <64cd759b-d2c2-121d-b960-4a806b8da27a@gmail.com> In-Reply-To: <64cd759b-d2c2-121d-b960-4a806b8da27a@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: list From: Robin Dapp via Gcc-patches <gcc-patches@gcc.gnu.org> Reply-To: Robin Dapp <rdapp.gcc@gmail.com> Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org>
Series	[v3] RISC-V: Add autovec FP unary operations. \| expand [v3] RISC-V: Add autovec FP unary operations.

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 94452c932a4..5b84eaaf052 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -513,7 +513,7 @@ (define_expand "<optab><mode>2" }) ;; ------------------------------------------------------------------------------- -;; - ABS expansion to vmslt and vneg +;; - [INT] ABS expansion to vmslt and vneg. ;; ------------------------------------------------------------------------------- (define_expand "abs<mode>2" @@ -532,6 +532,40 @@ (define_expand "abs<mode>2" DONE; }) +;; ------------------------------------------------------------------------------- +;; ---- [FP] Unary operations +;; ------------------------------------------------------------------------------- +;; Includes: +;; - vfneg.v/vfabs.v +;; ------------------------------------------------------------------------------- +(define_expand "<optab><mode>2" + [(set (match_operand:VF_AUTO 0 "register_operand") + (any_float_unop_nofrm:VF_AUTO + (match_operand:VF_AUTO 1 "register_operand")))] + "TARGET_VECTOR" +{ + insn_code icode = code_for_pred (<CODE>, <MODE>mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands); + DONE; +}) + +;; ------------------------------------------------------------------------------- +;; - [FP] Square root +;; ------------------------------------------------------------------------------- +;; Includes: +;; - vfsqrt.v +;; ------------------------------------------------------------------------------- +(define_expand "<optab><mode>2" + [(set (match_operand:VF_AUTO 0 "register_operand") + (any_float_unop:VF_AUTO + (match_operand:VF_AUTO 1 "register_operand")))] + "TARGET_VECTOR" +{ + insn_code icode = code_for_pred (<CODE>, <MODE>mode); + riscv_vector::emit_vlmax_fp_insn (icode, riscv_vector::RVV_UNOP, operands); + DONE; +}) + ;; ========================================================================= ;; == Ternary arithmetic ;; ========================================================================= diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c index d864b54229b..5575ece4599 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_vector } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "abs-template.h" @@ -7,30 +7,32 @@ #define SZ 128 -#define RUN(TYPE) \ - TYPE a##TYPE[SZ]; \ - for (int i = 0; i < SZ; i++) \ - { \ - if (i & 1) \ - a##TYPE[i] = i - 64; \ - else \ - a##TYPE[i] = i; \ - } \ - vabs_##TYPE (a##TYPE, a##TYPE, SZ); \ - for (int i = 0; i < SZ; i++) \ - { \ - if (i & 1) \ - assert (a##TYPE[i] == abs (i - 64)); \ - else \ - assert (a##TYPE[i] == i); \ +#define RUN(TYPE) \ + TYPE a##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + if (i & 1) \ + a##TYPE[i] = i - 64; \ + else \ + a##TYPE[i] = i; \ + } \ + vabs_##TYPE (a##TYPE, a##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + { \ + if (i & 1) \ + assert (a##TYPE[i] == __builtin_abs (i - 64)); \ + else \ + assert (a##TYPE[i] == i); \ } -#define RUN_ALL() \ - RUN(int8_t) \ - RUN(int16_t) \ - RUN(int32_t) \ - RUN(int64_t) +#define RUN_ALL() \ + RUN(int8_t) \ + RUN(int16_t) \ + RUN(int32_t) \ + RUN(int64_t) \ + RUN(float) \ + RUN(double) \ int main () { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c index a8b92c9450f..dea790ccc2d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c @@ -1,8 +1,9 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "abs-template.h" /* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,mu} 4 } } */ /* { dg-final { scan-assembler-times {\tvmslt\.vi} 4 } } */ /* { dg-final { scan-assembler-times {\tvneg.v\sv[0-9]+,v[0-9]+,v0\.t} 4 } } */ +/* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c index 2e7f0864ee7..b58f1aa3496 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c @@ -1,8 +1,9 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "abs-template.h" /* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,mu} 4 } } */ /* { dg-final { scan-assembler-times {\tvmslt\.vi} 4 } } */ /* { dg-final { scan-assembler-times {\tvneg.v\sv[0-9]+,v[0-9]+,v0\.t} 4 } } */ +/* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h index 882de9f4efb..08bd5b3629c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h @@ -6,7 +6,7 @@ void vabs_##TYPE (TYPE *dst, TYPE *a, int n) \ { \ for (int i = 0; i < n; i++) \ - dst[i] = abs (a[i]); \ + dst[i] = __builtin_abs (a[i]); \ } #define TEST_TYPE2(TYPE) \ @@ -14,13 +14,24 @@ void vabs_##TYPE (TYPE *dst, TYPE *a, int n) \ { \ for (int i = 0; i < n; i++) \ - dst[i] = llabs (a[i]); \ + dst[i] = __builtin_llabs (a[i]); \ + } + +#define TEST_TYPE3(TYPE) \ + __attribute__((noipa)) \ + void vabs_##TYPE (TYPE *dst, TYPE *a, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = __builtin_fabs (a[i]); \ } #define TEST_ALL() \ TEST_TYPE(int8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(int32_t) \ - TEST_TYPE2(int64_t) + TEST_TYPE2(int64_t) \ + TEST_TYPE3(_Float16) \ + TEST_TYPE3(float) \ + TEST_TYPE3(double) \ TEST_ALL() diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c new file mode 100644 index 00000000000..65087d51665 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c @@ -0,0 +1,35 @@ +/* { dg-do run { target { riscv_zvfh_hw } } } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ + +#include "abs-template.h" + +#include <assert.h> + +#define SZ 128 + +#define RUN(TYPE) \ + TYPE a##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + if (i & 1) \ + a##TYPE[i] = i - 64; \ + else \ + a##TYPE[i] = i; \ + } \ + vabs_##TYPE (a##TYPE, a##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + { \ + if (i & 1) \ + assert (a##TYPE[i] == __builtin_abs (i - 64)); \ + else \ + assert (a##TYPE[i] == i); \ + } + + +#define RUN_ALL() \ + RUN(_Float16) \ + +int main () +{ + RUN_ALL() +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c new file mode 100644 index 00000000000..01a518451e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ + +#include "vfsqrt-template.h" + +#include <assert.h> + +#define SZ 255 + +#define EPS 1e-5 + +#define RUN(TYPE) \ + TYPE a##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE[i] = (TYPE)i; \ + } \ + vsqrt_##TYPE (a##TYPE, a##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (__builtin_fabs \ + (a##TYPE[i] - __builtin_sqrtf ((TYPE)i)) < EPS); \ + +#define RUN_ALL() \ + RUN(float) \ + RUN(double) \ + +int main () +{ + RUN_ALL() +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c new file mode 100644 index 00000000000..a1874c8f9f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ + +#include "vfsqrt-template.h" + +/* We cannot link this without the Zvfh extension so define + it here instead of in the template directly (which is also + included by the run test that might need to be linked without + the extension). */ +TEST_TYPE3(_Float16) + +/* { dg-final { scan-assembler-times {\tvfsqrt\.v} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c new file mode 100644 index 00000000000..955621d4bcd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ + +#include "vfsqrt-template.h" + +/* We cannot link this without the Zvfh extension so define + it here instead of in the template directly (which is also + included by the run test that might need to be linked without + the extension). */ +TEST_TYPE3(_Float16) + +/* { dg-final { scan-assembler-times {\tvfsqrt\.v} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h new file mode 100644 index 00000000000..314ea646bec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h @@ -0,0 +1,31 @@ +#include <stdint-gcc.h> + +#define TEST_TYPE(TYPE) \ + __attribute__((noipa)) \ + void vsqrt_##TYPE (TYPE *dst, TYPE *a, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = __builtin_sqrtf (a[i]); \ + } + +#define TEST_TYPE2(TYPE) \ + __attribute__((noipa)) \ + void vsqrt_##TYPE (TYPE *dst, TYPE *a, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = __builtin_sqrt (a[i]); \ + } + +#define TEST_TYPE3(TYPE) \ + __attribute__((noipa)) \ + void vsqrt_##TYPE (TYPE *dst, TYPE *a, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = __builtin_sqrtf16 (a[i]); \ + } + +#define TEST_ALL() \ + TEST_TYPE(float) \ + TEST_TYPE2(double) \ + +TEST_ALL() diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c new file mode 100644 index 00000000000..5849e486047 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c @@ -0,0 +1,33 @@ +/* { dg-do run { target { riscv_zvfh_hw } } } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ + +#include "vfsqrt-template.h" + +/* We cannot link this without the Zvfh extension so define + it here instead of in the template directly. */ +TEST_TYPE3(_Float16) + +#include <assert.h> + +#define SZ 255 + +#define EPS 1e-5 + +#define RUN(TYPE) \ + TYPE a##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE[i] = (TYPE)i; \ + } \ + vsqrt_##TYPE (a##TYPE, a##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (__builtin_fabs \ + (a##TYPE[i] - __builtin_sqrtf ((TYPE)i)) < EPS); \ + +#define RUN_ALL() \ + RUN(_Float16) \ + +int main () +{ + RUN_ALL() +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c index abeb50f21ea..f9fb126b3b7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_vector } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "vneg-template.h" @@ -13,7 +13,7 @@ { \ a##TYPE[i] = i - 127; \ } \ - vneg_##TYPE (a##TYPE, a##TYPE, SZ); \ + vneg_##TYPE (a##TYPE, a##TYPE, SZ); \ for (int i = 0; i < SZ; i++) \ assert (a##TYPE[i] == -(i - 127)); @@ -21,7 +21,9 @@ RUN(int8_t) \ RUN(int16_t) \ RUN(int32_t) \ - RUN(int64_t) + RUN(int64_t) \ + RUN(float) \ + RUN(double) \ int main () { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c index 69d9ebb0953..4a9ceb5faf2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "vneg-template.h" /* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */ +/* { dg-final { scan-assembler-times {\tvfneg\.v} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c index d2c2e17c13e..2c5e2bd2a0b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "vneg-template.h" /* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */ +/* { dg-final { scan-assembler-times {\tvfneg\.v} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h index 93e690f3cec..892d9d72c38 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h @@ -13,6 +13,9 @@ TEST_TYPE(int8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(int32_t) \ - TEST_TYPE(int64_t) + TEST_TYPE(int64_t) \ + TEST_TYPE(_Float16) \ + TEST_TYPE(float) \ + TEST_TYPE(double) \ TEST_ALL() diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c new file mode 100644 index 00000000000..64c965fea1a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { riscv_zvfh_hw } } } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ + +#include "vneg-template.h" + +#include <assert.h> + +#define SZ 255 + +#define RUN(TYPE) \ + TYPE a##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE[i] = i - 127; \ + } \ + vneg_##TYPE (a##TYPE, a##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (a##TYPE[i] == -(i - 127)); + +#define RUN_ALL() \ + RUN(_Float16) \ + +int main () +{ + RUN_ALL() +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c index 08da48d0270..109fcbcaf00 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c @@ -31,5 +31,19 @@ void f4 (_Float16 * __restrict a, _Float16 * __restrict b, int n) a[i] = a[i]/b[i]; } -/* We can't enable FP16 NEG/PLUS/MINUS/MULT/DIV auto-vectorization when -march="*zvfhmin*". */ +void f6 (_Float16 * __restrict a, _Float16 * __restrict b, int n) +{ + for (int i = 0; i < n; i++) + a[i] = __builtin_fabs (b[i]); +} + +void f7 (_Float16 * __restrict a, _Float16 * __restrict b, int n) +{ + for (int i = 0; i < n; i++) + a[i] = __builtin_sqrtf (b[i]); +} + +/* We can't enable FP16 NEG/PLUS/MINUS/MULT/DIV/ABS/SQRTF auto-vectorization + when -march="*zvfhmin*" because the min variant of the extension only + provides loads, stores and conversions. */ /* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 0 "vect" } } */

[v3] RISC-V: Add autovec FP unary operations.

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