diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 9fa8cf89f61..bd79a3f9e84 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -2650,10 +2650,10 @@ (define_expand "cbranchv16qi4"
 ;; Compare vectors producing a vector result and a predicate, setting CR6 to
 ;; indicate a combined status
 (define_insn "altivec_vcmpequ<VI_char>_p"
-  [(set (reg:CC CR6_REGNO)
-	(unspec:CC [(eq:CC (match_operand:VI2 1 "register_operand" "v")
-			   (match_operand:VI2 2 "register_operand" "v"))]
-		   UNSPEC_PREDICATE))
+  [(set (reg:CCLTEQ CR6_REGNO)
+	(unspec:CCLTEQ [(eq:CC (match_operand:VI2 1 "register_operand" "v")
+			       (match_operand:VI2 2 "register_operand" "v"))]
+		       UNSPEC_PREDICATE))
    (set (match_operand:VI2 0 "register_operand" "=v")
 	(eq:VI2 (match_dup 1)
 		(match_dup 2)))]
@@ -2662,10 +2662,11 @@ (define_insn "altivec_vcmpequ<VI_char>_p"
   [(set_attr "type" "veccmpfx")])

 (define_insn "altivec_vcmpequt_p"
-  [(set (reg:CC CR6_REGNO)
-	(unspec:CC [(eq:CC (match_operand:V1TI 1 "altivec_register_operand" "v")
-			   (match_operand:V1TI 2 "altivec_register_operand" "v"))]
-		   UNSPEC_PREDICATE))
+  [(set (reg:CCLTEQ CR6_REGNO)
+	(unspec:CCLTEQ
+	  [(eq:CC (match_operand:V1TI 1 "altivec_register_operand" "v")
+		  (match_operand:V1TI 2 "altivec_register_operand" "v"))]
+	  UNSPEC_PREDICATE))
    (set (match_operand:V1TI 0 "altivec_register_operand" "=v")
 	(eq:V1TI (match_dup 1)
 		 (match_dup 2)))]
@@ -2686,10 +2687,10 @@ (define_expand "altivec_vcmpne_<mode>"
   })

 (define_insn "*altivec_vcmpgts<VI_char>_p"
-  [(set (reg:CC CR6_REGNO)
-	(unspec:CC [(gt:CC (match_operand:VI2 1 "register_operand" "v")
-			   (match_operand:VI2 2 "register_operand" "v"))]
-		   UNSPEC_PREDICATE))
+  [(set (reg:CCLTEQ CR6_REGNO)
+	(unspec:CCLTEQ [(gt:CC (match_operand:VI2 1 "register_operand" "v")
+			       (match_operand:VI2 2 "register_operand" "v"))]
+		       UNSPEC_PREDICATE))
    (set (match_operand:VI2 0 "register_operand" "=v")
 	(gt:VI2 (match_dup 1)
 		(match_dup 2)))]
@@ -2698,10 +2699,10 @@ (define_insn "*altivec_vcmpgts<VI_char>_p"
   [(set_attr "type" "veccmpfx")])

 (define_insn "*altivec_vcmpgtst_p"
-  [(set (reg:CC CR6_REGNO)
-	(unspec:CC [(gt:CC (match_operand:V1TI 1 "register_operand" "v")
-			   (match_operand:V1TI 2 "register_operand" "v"))]
-		   UNSPEC_PREDICATE))
+  [(set (reg:CCLTEQ CR6_REGNO)
+	(unspec:CCLTEQ [(gt:CC (match_operand:V1TI 1 "register_operand" "v")
+			       (match_operand:V1TI 2 "register_operand" "v"))]
+		       UNSPEC_PREDICATE))
    (set (match_operand:V1TI 0 "register_operand" "=v")
 	(gt:V1TI (match_dup 1)
 		 (match_dup 2)))]
@@ -2710,10 +2711,10 @@ (define_insn "*altivec_vcmpgtst_p"
   [(set_attr "type" "veccmpfx")])

 (define_insn "*altivec_vcmpgtu<VI_char>_p"
-  [(set (reg:CC CR6_REGNO)
-	(unspec:CC [(gtu:CC (match_operand:VI2 1 "register_operand" "v")
-			    (match_operand:VI2 2 "register_operand" "v"))]
-		   UNSPEC_PREDICATE))
+  [(set (reg:CCLTEQ CR6_REGNO)
+	(unspec:CCLTEQ [(gtu:CC (match_operand:VI2 1 "register_operand" "v")
+				(match_operand:VI2 2 "register_operand" "v"))]
+		       UNSPEC_PREDICATE))
    (set (match_operand:VI2 0 "register_operand" "=v")
 	(gtu:VI2 (match_dup 1)
 		 (match_dup 2)))]
@@ -2722,10 +2723,10 @@ (define_insn "*altivec_vcmpgtu<VI_char>_p"
   [(set_attr "type" "veccmpfx")])

 (define_insn "*altivec_vcmpgtut_p"
-  [(set (reg:CC CR6_REGNO)
-	(unspec:CC [(gtu:CC (match_operand:V1TI 1 "register_operand" "v")
-			    (match_operand:V1TI 2 "register_operand" "v"))]
-		   UNSPEC_PREDICATE))
+  [(set (reg:CCLTEQ CR6_REGNO)
+	(unspec:CCLTEQ [(gtu:CC (match_operand:V1TI 1 "register_operand" "v")
+				(match_operand:V1TI 2 "register_operand" "v"))]
+		       UNSPEC_PREDICATE))
    (set (match_operand:V1TI 0 "register_operand" "=v")
 	(gtu:V1TI (match_dup 1)
 		  (match_dup 2)))]
@@ -2734,10 +2735,10 @@ (define_insn "*altivec_vcmpgtut_p"
   [(set_attr "type" "veccmpfx")])

 (define_insn "*altivec_vcmpeqfp_p"
-  [(set (reg:CC CR6_REGNO)
-	(unspec:CC [(eq:CC (match_operand:V4SF 1 "register_operand" "v")
-			   (match_operand:V4SF 2 "register_operand" "v"))]
-		   UNSPEC_PREDICATE))
+  [(set (reg:CCLTEQ CR6_REGNO)
+	(unspec:CCLTEQ [(eq:CC (match_operand:V4SF 1 "register_operand" "v")
+			       (match_operand:V4SF 2 "register_operand" "v"))]
+		       UNSPEC_PREDICATE))
    (set (match_operand:V4SF 0 "register_operand" "=v")
 	(eq:V4SF (match_dup 1)
 		 (match_dup 2)))]
@@ -2746,10 +2747,10 @@ (define_insn "*altivec_vcmpeqfp_p"
   [(set_attr "type" "veccmp")])

 (define_insn "*altivec_vcmpgtfp_p"
-  [(set (reg:CC CR6_REGNO)
-	(unspec:CC [(gt:CC (match_operand:V4SF 1 "register_operand" "v")
-			   (match_operand:V4SF 2 "register_operand" "v"))]
-		   UNSPEC_PREDICATE))
+  [(set (reg:CCLTEQ CR6_REGNO)
+	(unspec:CCLTEQ [(gt:CC (match_operand:V4SF 1 "register_operand" "v")
+			       (match_operand:V4SF 2 "register_operand" "v"))]
+		       UNSPEC_PREDICATE))
    (set (match_operand:V4SF 0 "register_operand" "=v")
 	(gt:V4SF (match_dup 1)
 		 (match_dup 2)))]
@@ -2758,10 +2759,10 @@ (define_insn "*altivec_vcmpgtfp_p"
   [(set_attr "type" "veccmp")])

 (define_insn "*altivec_vcmpgefp_p"
-  [(set (reg:CC CR6_REGNO)
-	(unspec:CC [(ge:CC (match_operand:V4SF 1 "register_operand" "v")
-			   (match_operand:V4SF 2 "register_operand" "v"))]
-		   UNSPEC_PREDICATE))
+  [(set (reg:CCLTEQ CR6_REGNO)
+	(unspec:CCLTEQ [(ge:CC (match_operand:V4SF 1 "register_operand" "v")
+			       (match_operand:V4SF 2 "register_operand" "v"))]
+		       UNSPEC_PREDICATE))
    (set (match_operand:V4SF 0 "register_operand" "=v")
 	(ge:V4SF (match_dup 1)
 		 (match_dup 2)))]
@@ -2770,10 +2771,10 @@ (define_insn "*altivec_vcmpgefp_p"
   [(set_attr "type" "veccmp")])

 (define_insn "altivec_vcmpbfp_p"
-  [(set (reg:CC CR6_REGNO)
-	(unspec:CC [(match_operand:V4SF 1 "register_operand" "v")
-		    (match_operand:V4SF 2 "register_operand" "v")]
-		   UNSPEC_VCMPBFP))
+  [(set (reg:CCLTEQ CR6_REGNO)
+	(unspec:CCLTEQ [(match_operand:V4SF 1 "register_operand" "v")
+			(match_operand:V4SF 2 "register_operand" "v")]
+		       UNSPEC_VCMPBFP))
    (set (match_operand:V4SF 0 "register_operand" "=v")
         (unspec:V4SF [(match_dup 1)
                       (match_dup 2)]
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 18198add744..322e7639fd4 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -1352,7 +1352,9 @@ (define_predicate "branch_comparison_operator"
 	    (match_code "lt,gt,eq,unordered,unge,unle,ne,ordered"))
 	  (if_then_else (match_test "GET_MODE (XEXP (op, 0)) == CCBCDmode")
 	    (match_code "lt,le,gt,ge,eq,ne,unordered,ordered")
-	    (match_code "lt,ltu,le,leu,gt,gtu,ge,geu,eq,ne")))
+	    (if_then_else (match_test "GET_MODE (XEXP (op, 0)) == CCLTEQmode")
+	       (match_code "lt,ge,eq,ne")
+	       (match_code "lt,ltu,le,leu,gt,gtu,ge,geu,eq,ne"))))
 	(match_test "validate_condition_mode (GET_CODE (op),
 					      GET_MODE (XEXP (op, 0))),
 		     1")))
diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def
index 3e2e6dfb4ff..9c2e2432957 100644
--- a/gcc/config/rs6000/rs6000-modes.def
+++ b/gcc/config/rs6000/rs6000-modes.def
@@ -62,6 +62,7 @@ FRACTIONAL_FLOAT_MODE (TF, FLOAT_PRECISION_TFmode, 16, ieee_quad_format);
 CC_MODE (CCUNS);
 CC_MODE (CCFP);
 CC_MODE (CCBCD);	/* Used for bcd insns */
+CC_MODE (CCLTEQ);	/* Used for the case only checks cr bit 0 and bit 2 */
 CC_MODE (CCEQ);

 /* Vector modes.  */
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 4068cd8b929..97023ebe323 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -11594,6 +11594,9 @@ validate_condition_mode (enum rtx_code code, machine_mode mode)
   gcc_assert ((code != GT && code != LT && code != GE && code != LE)
 	      || mode != CCUNSmode);

+  gcc_assert (mode != CCLTEQmode
+	      || (code != GT && code != LE));
+
   gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
 	      || mode == CCUNSmode);

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 9b5fcdc8db0..2c6255395d1 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -8115,7 +8115,7 @@ (define_expand "movcc"
   ""
   "")

-(define_mode_iterator CC_any [CC CCUNS CCEQ CCFP CCBCD])
+(define_mode_iterator CC_any [CC CCUNS CCEQ CCFP CCBCD CCLTEQ])

 (define_insn "*movcc_<mode>"
   [(set (match_operand:CC_any 0 "nonimmediate_operand"
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index f9796fb3781..f86c1f2990e 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -888,10 +888,10 @@ (define_expand "vector_select_<mode>_uns"
 ;; setting CR6 to indicate a combined status
 (define_expand "vector_eq_<mode>_p"
   [(parallel
-    [(set (reg:CC CR6_REGNO)
-	  (unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand")
-			     (match_operand:VEC_A 2 "vlogical_operand"))]
-		     UNSPEC_PREDICATE))
+    [(set (reg:CCLTEQ CR6_REGNO)
+	  (unspec:CCLTEQ [(eq:CC (match_operand:VEC_A 1 "vlogical_operand")
+				 (match_operand:VEC_A 2 "vlogical_operand"))]
+			 UNSPEC_PREDICATE))
      (set (match_operand:VEC_A 0 "vlogical_operand")
 	  (eq:VEC_A (match_dup 1)
 		    (match_dup 2)))])]
@@ -900,10 +900,11 @@ (define_expand "vector_eq_<mode>_p"

 (define_expand "vector_eq_v1ti_p"
   [(parallel
-    [(set (reg:CC CR6_REGNO)
-	  (unspec:CC [(eq:CC (match_operand:V1TI 1 "altivec_register_operand")
-			     (match_operand:V1TI 2 "altivec_register_operand"))]
-		     UNSPEC_PREDICATE))
+    [(set (reg:CCLTEQ CR6_REGNO)
+	  (unspec:CCLTEQ
+	     [(eq:CC (match_operand:V1TI 1 "altivec_register_operand")
+		     (match_operand:V1TI 2 "altivec_register_operand"))]
+	     UNSPEC_PREDICATE))
      (set (match_operand:V1TI 0 "vlogical_operand")
 	  (eq:V1TI (match_dup 1)
 		   (match_dup 2)))])]
@@ -914,15 +915,15 @@ (define_expand "vector_eq_v1ti_p"
 ;; implementation of the vec_all_ne built-in functions on Power9.
 (define_expand "vector_ne_<mode>_p"
   [(parallel
-    [(set (reg:CC CR6_REGNO)
-	  (unspec:CC [(ne:CC (match_operand:VI 1 "vlogical_operand")
-			     (match_operand:VI 2 "vlogical_operand"))]
+    [(set (reg:CCLTEQ CR6_REGNO)
+	  (unspec:CCLTEQ [(ne:CC (match_operand:VI 1 "vlogical_operand")
+			  (match_operand:VI 2 "vlogical_operand"))]
 	   UNSPEC_PREDICATE))
      (set (match_dup 3)
 	  (ne:VI (match_dup 1)
 		 (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
-	(lt:SI (reg:CC CR6_REGNO)
+	(lt:SI (reg:CCLTEQ CR6_REGNO)
 	       (const_int 0)))]
   "TARGET_P9_VECTOR"
 {
@@ -933,15 +934,15 @@ (define_expand "vector_ne_<mode>_p"
 ;; implementation of the vec_any_eq built-in functions on Power9.
 (define_expand "vector_ae_<mode>_p"
   [(parallel
-    [(set (reg:CC CR6_REGNO)
-	  (unspec:CC [(ne:CC (match_operand:VI 1 "vlogical_operand")
-			     (match_operand:VI 2 "vlogical_operand"))]
+    [(set (reg:CCLTEQ CR6_REGNO)
+	  (unspec:CCLTEQ [(ne:CC (match_operand:VI 1 "vlogical_operand")
+				 (match_operand:VI 2 "vlogical_operand"))]
 	   UNSPEC_PREDICATE))
      (set (match_dup 3)
 	  (ne:VI (match_dup 1)
 		 (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
-	(lt:SI (reg:CC CR6_REGNO)
+	(lt:SI (reg:CCLTEQ CR6_REGNO)
 	       (const_int 0)))
    (set (match_dup 0)
 	(xor:SI (match_dup 0)
@@ -956,11 +957,11 @@ (define_expand "vector_ae_<mode>_p"
 ;; functions on Power9.
 (define_expand "vector_nez_<mode>_p"
   [(parallel
-    [(set (reg:CC CR6_REGNO)
-	  (unspec:CC [(unspec:VI
-		       [(match_operand:VI 1 "vlogical_operand")
-			(match_operand:VI 2 "vlogical_operand")]
-		       UNSPEC_NEZ_P)]
+    [(set (reg:CCLTEQ CR6_REGNO)
+	  (unspec:CCLTEQ [(unspec:VI
+			  [(match_operand:VI 1 "vlogical_operand")
+			   (match_operand:VI 2 "vlogical_operand")]
+			 UNSPEC_NEZ_P)]
 	   UNSPEC_PREDICATE))
      (set (match_operand:VI 0 "vlogical_operand")
 	  (unspec:VI [(match_dup 1)
@@ -977,15 +978,15 @@ (define_expand "vector_nez_<mode>_p"
 ;; architecture.
 (define_expand "vector_ne_v2di_p"
   [(parallel
-    [(set (reg:CC CR6_REGNO)
-	  (unspec:CC [(eq:CC (match_operand:V2DI 1 "vlogical_operand")
-			     (match_operand:V2DI 2 "vlogical_operand"))]
-		     UNSPEC_PREDICATE))
+    [(set (reg:CCLTEQ CR6_REGNO)
+	  (unspec:CCLTEQ [(eq:CC (match_operand:V2DI 1 "vlogical_operand")
+				 (match_operand:V2DI 2 "vlogical_operand"))]
+			 UNSPEC_PREDICATE))
      (set (match_dup 3)
 	  (eq:V2DI (match_dup 1)
 		   (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
-	(eq:SI (reg:CC CR6_REGNO)
+	(eq:SI (reg:CCLTEQ CR6_REGNO)
 	       (const_int 0)))]
   "TARGET_P9_VECTOR"
 {
@@ -994,15 +995,16 @@ (define_expand "vector_ne_v2di_p"

 (define_expand "vector_ne_v1ti_p"
   [(parallel
-    [(set (reg:CC CR6_REGNO)
-	  (unspec:CC [(eq:CC (match_operand:V1TI 1 "altivec_register_operand")
-			     (match_operand:V1TI 2 "altivec_register_operand"))]
-		     UNSPEC_PREDICATE))
+    [(set (reg:CCLTEQ CR6_REGNO)
+	  (unspec:CCLTEQ
+	    [(eq:CC (match_operand:V1TI 1 "altivec_register_operand")
+		    (match_operand:V1TI 2 "altivec_register_operand"))]
+	    UNSPEC_PREDICATE))
      (set (match_dup 3)
 	  (eq:V1TI (match_dup 1)
 		   (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
-	(eq:SI (reg:CC CR6_REGNO)
+	(eq:SI (reg:CCLTEQ CR6_REGNO)
 	       (const_int 0)))]
   "TARGET_POWER10"
 {
@@ -1017,15 +1019,15 @@ (define_expand "vector_ne_v1ti_p"
 ;; architecture.
 (define_expand "vector_ae_v2di_p"
   [(parallel
-    [(set (reg:CC CR6_REGNO)
-	  (unspec:CC [(eq:CC (match_operand:V2DI 1 "vlogical_operand")
-			     (match_operand:V2DI 2 "vlogical_operand"))]
-		     UNSPEC_PREDICATE))
+    [(set (reg:CCLTEQ CR6_REGNO)
+	  (unspec:CCLTEQ [(eq:CC (match_operand:V2DI 1 "vlogical_operand")
+				 (match_operand:V2DI 2 "vlogical_operand"))]
+			 UNSPEC_PREDICATE))
      (set (match_dup 3)
 	  (eq:V2DI (match_dup 1)
 		   (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
-	(eq:SI (reg:CC CR6_REGNO)
+	(eq:SI (reg:CCLTEQ CR6_REGNO)
 	       (const_int 0)))
    (set (match_dup 0)
 	(xor:SI (match_dup 0)
@@ -1037,15 +1039,16 @@ (define_expand "vector_ae_v2di_p"

 (define_expand "vector_ae_v1ti_p"
   [(parallel
-    [(set (reg:CC CR6_REGNO)
-	  (unspec:CC [(eq:CC (match_operand:V1TI 1 "altivec_register_operand")
-			     (match_operand:V1TI 2 "altivec_register_operand"))]
-		     UNSPEC_PREDICATE))
+    [(set (reg:CCLTEQ CR6_REGNO)
+	  (unspec:CCLTEQ
+	    [(eq:CC (match_operand:V1TI 1 "altivec_register_operand")
+		    (match_operand:V1TI 2 "altivec_register_operand"))]
+	    UNSPEC_PREDICATE))
      (set (match_dup 3)
 	  (eq:V1TI (match_dup 1)
 		   (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
-	(eq:SI (reg:CC CR6_REGNO)
+	(eq:SI (reg:CCLTEQ CR6_REGNO)
 	       (const_int 0)))
    (set (match_dup 0)
 	(xor:SI (match_dup 0)
@@ -1062,15 +1065,15 @@ (define_expand "vector_ae_v1ti_p"
 ;; for vector compare not equal with floating point arguments.
 (define_expand "vector_ne_<mode>_p"
   [(parallel
-    [(set (reg:CC CR6_REGNO)
-	  (unspec:CC [(eq:CC (match_operand:VEC_F 1 "vlogical_operand")
-			     (match_operand:VEC_F 2 "vlogical_operand"))]
-		     UNSPEC_PREDICATE))
+    [(set (reg:CCLTEQ CR6_REGNO)
+	  (unspec:CCLTEQ [(eq:CC (match_operand:VEC_F 1 "vlogical_operand")
+				 (match_operand:VEC_F 2 "vlogical_operand"))]
+			 UNSPEC_PREDICATE))
      (set (match_dup 3)
 	  (eq:VEC_F (match_dup 1)
 		    (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
-	(eq:SI (reg:CC CR6_REGNO)
+	(eq:SI (reg:CCLTEQ CR6_REGNO)
 	       (const_int 0)))]
   "TARGET_P9_VECTOR"
 {
@@ -1084,15 +1087,15 @@ (define_expand "vector_ne_<mode>_p"
 ;; for vector compare not equal with floating point arguments.
 (define_expand "vector_ae_<mode>_p"
   [(parallel
-    [(set (reg:CC CR6_REGNO)
-	  (unspec:CC [(eq:CC (match_operand:VEC_F 1 "vlogical_operand")
-			     (match_operand:VEC_F 2 "vlogical_operand"))]
-		     UNSPEC_PREDICATE))
+    [(set (reg:CCLTEQ CR6_REGNO)
+	  (unspec:CCLTEQ [(eq:CC (match_operand:VEC_F 1 "vlogical_operand")
+				 (match_operand:VEC_F 2 "vlogical_operand"))]
+			 UNSPEC_PREDICATE))
      (set (match_dup 3)
 	  (eq:VEC_F (match_dup 1)
 		    (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
-	(eq:SI (reg:CC CR6_REGNO)
+	(eq:SI (reg:CCLTEQ CR6_REGNO)
 	       (const_int 0)))
    (set (match_dup 0)
 	(xor:SI (match_dup 0)
@@ -1104,10 +1107,10 @@ (define_expand "vector_ae_<mode>_p"

 (define_expand "vector_gt_<mode>_p"
   [(parallel
-    [(set (reg:CC CR6_REGNO)
-	  (unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand")
-			     (match_operand:VEC_A 2 "vlogical_operand"))]
-		     UNSPEC_PREDICATE))
+    [(set (reg:CCLTEQ CR6_REGNO)
+	  (unspec:CCLTEQ [(gt:CC (match_operand:VEC_A 1 "vlogical_operand")
+				 (match_operand:VEC_A 2 "vlogical_operand"))]
+			 UNSPEC_PREDICATE))
      (set (match_operand:VEC_A 0 "vlogical_operand")
 	  (gt:VEC_A (match_dup 1)
 		    (match_dup 2)))])]
@@ -1116,10 +1119,10 @@ (define_expand "vector_gt_<mode>_p"

 (define_expand "vector_gt_v1ti_p"
   [(parallel
-    [(set (reg:CC CR6_REGNO)
-	  (unspec:CC [(gt:CC (match_operand:V1TI 1 "vlogical_operand")
-			     (match_operand:V1TI 2 "vlogical_operand"))]
-		     UNSPEC_PREDICATE))
+    [(set (reg:CCLTEQ CR6_REGNO)
+	  (unspec:CCLTEQ [(gt:CC (match_operand:V1TI 1 "vlogical_operand")
+				 (match_operand:V1TI 2 "vlogical_operand"))]
+			 UNSPEC_PREDICATE))
      (set (match_operand:V1TI 0 "vlogical_operand")
 	  (gt:V1TI (match_dup 1)
 		   (match_dup 2)))])]
@@ -1128,10 +1131,10 @@ (define_expand "vector_gt_v1ti_p"

 (define_expand "vector_ge_<mode>_p"
   [(parallel
-    [(set (reg:CC CR6_REGNO)
-	  (unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand")
-			     (match_operand:VEC_F 2 "vfloat_operand"))]
-		     UNSPEC_PREDICATE))
+    [(set (reg:CCLTEQ CR6_REGNO)
+	  (unspec:CCLTEQ [(ge:CC (match_operand:VEC_F 1 "vfloat_operand")
+				 (match_operand:VEC_F 2 "vfloat_operand"))]
+			 UNSPEC_PREDICATE))
      (set (match_operand:VEC_F 0 "vfloat_operand")
 	  (ge:VEC_F (match_dup 1)
 		    (match_dup 2)))])]
@@ -1140,10 +1143,10 @@ (define_expand "vector_ge_<mode>_p"

 (define_expand "vector_gtu_<mode>_p"
   [(parallel
-    [(set (reg:CC CR6_REGNO)
-	  (unspec:CC [(gtu:CC (match_operand:VEC_IC 1 "vint_operand")
-			      (match_operand:VEC_IC 2 "vint_operand"))]
-		     UNSPEC_PREDICATE))
+    [(set (reg:CCLTEQ CR6_REGNO)
+	  (unspec:CCLTEQ [(gtu:CC (match_operand:VEC_IC 1 "vint_operand")
+				  (match_operand:VEC_IC 2 "vint_operand"))]
+			 UNSPEC_PREDICATE))
      (set (match_operand:VEC_IC 0 "vlogical_operand")
 	  (gtu:VEC_IC (match_dup 1)
 		      (match_dup 2)))])]
@@ -1158,7 +1161,7 @@ (define_expand "vector_gtu_<mode>_p"
 ;; integer constant first argument equals zero (aka __CR6_EQ in altivec.h).
 (define_expand "cr6_test_for_zero"
   [(set (match_operand:SI 0 "register_operand" "=r")
-	(eq:SI (reg:CC CR6_REGNO)
+	(eq:SI (reg:CCLTEQ CR6_REGNO)
 	       (const_int 0)))]
   "TARGET_ALTIVEC || TARGET_VSX"
   "")
@@ -1169,7 +1172,7 @@ (define_expand "cr6_test_for_zero"
 ;; integer constant first argument equals one (aka __CR6_EQ_REV in altivec.h).
 (define_expand "cr6_test_for_zero_reverse"
   [(set (match_operand:SI 0 "register_operand" "=r")
-	(eq:SI (reg:CC CR6_REGNO)
+	(eq:SI (reg:CCLTEQ CR6_REGNO)
 	       (const_int 0)))
    (set (match_dup 0)
 	(xor:SI (match_dup 0)
@@ -1183,7 +1186,7 @@ (define_expand "cr6_test_for_zero_reverse"
 ;; integer constant first argument equals two (aka __CR6_LT in altivec.h).
 (define_expand "cr6_test_for_lt"
   [(set (match_operand:SI 0 "register_operand" "=r")
-	(lt:SI (reg:CC CR6_REGNO)
+	(lt:SI (reg:CCLTEQ CR6_REGNO)
 	       (const_int 0)))]
   "TARGET_ALTIVEC || TARGET_VSX"
   "")
@@ -1195,7 +1198,7 @@ (define_expand "cr6_test_for_lt"
 ;; (aka __CR6_LT_REV in altivec.h).
 (define_expand "cr6_test_for_lt_reverse"
   [(set (match_operand:SI 0 "register_operand" "=r")
-	(lt:SI (reg:CC CR6_REGNO)
+	(lt:SI (reg:CCLTEQ CR6_REGNO)
 	       (const_int 0)))
    (set (match_dup 0)
 	(xor:SI (match_dup 0)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index f135fa079bd..58d8ef1ad18 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -2180,8 +2180,8 @@ (define_insn "*vsx_ge<mode>"
 ;; Compare vectors producing a vector result and a predicate, setting CR6 to
 ;; indicate a combined status
 (define_insn "*vsx_eq_<mode>_p"
-  [(set (reg:CC CR6_REGNO)
-	(unspec:CC
+  [(set (reg:CCLTEQ CR6_REGNO)
+	(unspec:CCLTEQ
 	 [(eq:CC (match_operand:VSX_F 1 "vsx_register_operand" "wa")
 		 (match_operand:VSX_F 2 "vsx_register_operand" "wa"))]
 	 UNSPEC_PREDICATE))
@@ -2193,8 +2193,8 @@ (define_insn "*vsx_eq_<mode>_p"
   [(set_attr "type" "<VStype_simple>")])

 (define_insn "*vsx_gt_<mode>_p"
-  [(set (reg:CC CR6_REGNO)
-	(unspec:CC
+  [(set (reg:CCLTEQ CR6_REGNO)
+	(unspec:CCLTEQ
 	 [(gt:CC (match_operand:VSX_F 1 "vsx_register_operand" "wa")
 		 (match_operand:VSX_F 2 "vsx_register_operand" "wa"))]
 	 UNSPEC_PREDICATE))
@@ -2245,8 +2245,8 @@ (define_expand "xvtlsbbz"
 })

 (define_insn "*vsx_ge_<mode>_p"
-  [(set (reg:CC CR6_REGNO)
-	(unspec:CC
+  [(set (reg:CCLTEQ CR6_REGNO)
+	(unspec:CCLTEQ
 	 [(ge:CC (match_operand:VSX_F 1 "vsx_register_operand" "wa")
 		 (match_operand:VSX_F 2 "vsx_register_operand" "wa"))]
 	 UNSPEC_PREDICATE))
@@ -5278,7 +5278,7 @@ (define_insn "*xscmpexpqp"
 ;;    are satisfied, and clearing the gt and undordered bits to zero.)
 (define_expand "xststdcqp_<mode>"
   [(set (match_dup 3)
-	(compare:CCFP
+	(compare:CCLTEQ
 	 (unspec:IEEE128
 	  [(match_operand:IEEE128 1 "altivec_register_operand" "v")
 	   (match_operand:SI 2 "u7bit_cint_operand" "n")]
@@ -5289,7 +5289,7 @@ (define_expand "xststdcqp_<mode>"
 	       (const_int 0)))]
   "TARGET_P9_VECTOR"
 {
-  operands[3] = gen_reg_rtx (CCFPmode);
+  operands[3] = gen_reg_rtx (CCLTEQmode);
 })

 ;; VSX Scalar Test Data Class Double- and Single-Precision
@@ -5298,7 +5298,7 @@ (define_expand "xststdcqp_<mode>"
 ;;   The gt and unordered bits are cleared to zero.)
 (define_expand "xststdc<sd>p"
   [(set (match_dup 3)
-	(compare:CCFP
+	(compare:CCLTEQ
 	 (unspec:SFDF
 	  [(match_operand:SFDF 1 "vsx_register_operand" "wa")
 	   (match_operand:SI 2 "u7bit_cint_operand" "n")]
@@ -5309,14 +5309,14 @@ (define_expand "xststdc<sd>p"
 	       (const_int 0)))]
   "TARGET_P9_VECTOR"
 {
-  operands[3] = gen_reg_rtx (CCFPmode);
+  operands[3] = gen_reg_rtx (CCLTEQmode);
   operands[4] = CONST0_RTX (SImode);
 })

 ;; The VSX Scalar Test Negative Quad-Precision
 (define_expand "xststdcnegqp_<mode>"
   [(set (match_dup 2)
-	(compare:CCFP
+	(compare:CCLTEQ
 	 (unspec:IEEE128
 	  [(match_operand:IEEE128 1 "altivec_register_operand" "v")
 	   (const_int 0)]
@@ -5327,13 +5327,13 @@ (define_expand "xststdcnegqp_<mode>"
 	       (const_int 0)))]
   "TARGET_P9_VECTOR"
 {
-  operands[2] = gen_reg_rtx (CCFPmode);
+  operands[2] = gen_reg_rtx (CCLTEQmode);
 })

 ;; The VSX Scalar Test Negative Double- and Single-Precision
 (define_expand "xststdcneg<sd>p"
   [(set (match_dup 2)
-	(compare:CCFP
+	(compare:CCLTEQ
 	 (unspec:SFDF
 	  [(match_operand:SFDF 1 "vsx_register_operand" "wa")
 	   (const_int 0)]
@@ -5344,13 +5344,13 @@ (define_expand "xststdcneg<sd>p"
 	       (const_int 0)))]
   "TARGET_P9_VECTOR"
 {
-  operands[2] = gen_reg_rtx (CCFPmode);
+  operands[2] = gen_reg_rtx (CCLTEQmode);
   operands[3] = CONST0_RTX (SImode);
 })

 (define_insn "*xststdcqp_<mode>"
-  [(set (match_operand:CCFP 0 "" "=y")
-	(compare:CCFP
+  [(set (match_operand:CCLTEQ 0 "" "=y")
+	(compare:CCLTEQ
 	 (unspec:IEEE128
 	  [(match_operand:IEEE128 1 "altivec_register_operand" "v")
 	   (match_operand:SI 2 "u7bit_cint_operand" "n")]
@@ -5361,8 +5361,8 @@ (define_insn "*xststdcqp_<mode>"
   [(set_attr "type" "fpcompare")])

 (define_insn "*xststdc<sd>p"
-  [(set (match_operand:CCFP 0 "" "=y")
-	(compare:CCFP
+  [(set (match_operand:CCLTEQ 0 "" "=y")
+	(compare:CCLTEQ
 	 (unspec:SFDF [(match_operand:SFDF 1 "vsx_register_operand" "wa")
 		       (match_operand:SI 2 "u7bit_cint_operand" "n")]
 	  UNSPEC_VSX_STSTDC)
@@ -5423,8 +5423,8 @@ (define_insn "xvtstdc<sd>p"
 ;; need to match v4sf, v2df, or v2di modes because those are expanded
 ;; to use Power8 instructions.
 (define_insn "*vsx_ne_<mode>_p"
-  [(set (reg:CC CR6_REGNO)
-	(unspec:CC
+  [(set (reg:CCLTEQ CR6_REGNO)
+	(unspec:CCLTEQ
 	 [(ne:CC (match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "v")
 		 (match_operand:VSX_EXTRACT_I 2 "gpc_reg_operand" "v"))]
 	 UNSPEC_PREDICATE))
@@ -5436,12 +5436,12 @@ (define_insn "*vsx_ne_<mode>_p"
   [(set_attr "type" "vecsimple")])

 (define_insn "*vector_nez_<mode>_p"
-  [(set (reg:CC CR6_REGNO)
-	(unspec:CC [(unspec:VI
-		     [(match_operand:VI 1 "gpc_reg_operand" "v")
-		      (match_operand:VI 2 "gpc_reg_operand" "v")]
-		     UNSPEC_NEZ_P)]
-	 UNSPEC_PREDICATE))
+  [(set (reg:CCLTEQ CR6_REGNO)
+	(unspec:CCLTEQ [(unspec:VI
+			[(match_operand:VI 1 "gpc_reg_operand" "v")
+			 (match_operand:VI 2 "gpc_reg_operand" "v")]
+			UNSPEC_NEZ_P)]
+		       UNSPEC_PREDICATE))
    (set (match_operand:VI 0 "gpc_reg_operand" "=v")
 	(unspec:VI [(match_dup 1)
 		    (match_dup 2)]
@@ -5807,8 +5807,8 @@ (define_insn "vcmpnezb"

 ;; Vector Compare Not Equal or Zero Byte predicate or record-form
 (define_insn "vcmpnezb_p"
-  [(set (reg:CC CR6_REGNO)
-	(unspec:CC
+  [(set (reg:CCLTEQ CR6_REGNO)
+	(unspec:CCLTEQ
 	 [(match_operand:V16QI 1 "altivec_register_operand" "v")
 	  (match_operand:V16QI 2 "altivec_register_operand" "v")]
 	 UNSPEC_VCMPNEZB))
