@@ -38,6 +38,8 @@
(define_mode_attr cas_short_expected_pred
[(QI "aarch64_reg_or_imm") (HI "aarch64_plushi_operand")])
+(define_mode_attr cas_short_expected_imm
+ [(QI "n") (HI "Uph")])
(define_insn_and_split "aarch64_compare_and_swap<mode>"
[(set (reg:CC CC_REGNUM) ;; bool out
@@ -47,7 +49,8 @@
(match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q"))) ;; memory
(set (match_dup 1)
(unspec_volatile:SHORT
- [(match_operand:SHORT 2 "<cas_short_expected_pred>" "rn") ;; expected
+ [(match_operand:SHORT 2 "<cas_short_expected_pred>"
+ "r<cas_short_expected_imm>") ;; expected
(match_operand:SHORT 3 "aarch64_reg_or_zero" "rZ") ;; desired
(match_operand:SI 4 "const_int_operand") ;; is_weak
(match_operand:SI 5 "const_int_operand") ;; mod_s
@@ -213,6 +213,13 @@
(and (match_code "const_int")
(match_test "(unsigned) exact_log2 (ival) <= 4")))
+(define_constraint "Uph"
+ "@internal
+ A constraint that matches HImode integers zero extendable to
+ SImode plus_operand."
+ (and (match_code "const_int")
+ (match_test "aarch64_plushi_immediate (op, VOIDmode)")))
+
(define_memory_constraint "Q"
"A memory address which uses a single base register with no offset."
(and (match_code "mem")
new file mode 100644
@@ -0,0 +1,25 @@
+/* PR target/94368 */
+/* { dg-do compile { target fpic } } */
+/* { dg-options "-fpic -O1 -fcommon" } */
+
+int b, c, d, e, f, h;
+short g;
+int foo (int) __attribute__ ((__const__));
+
+void
+bar (void)
+{
+ while (1)
+ {
+ while (1)
+ {
+ __atomic_load_n (&e, 0);
+ if (foo (2))
+ __sync_val_compare_and_swap (&c, 0, f);
+ b = 1;
+ if (h == e)
+ break;
+ }
+ __sync_val_compare_and_swap (&g, -1, f);
+ }
+}