From patchwork Wed Jan 10 19:05:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 1885081 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T9HMX4ByCz1yP3 for ; Thu, 11 Jan 2024 06:06:14 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5DBCB3858D38 for ; Wed, 10 Jan 2024 19:06:10 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id CD99E3858D38 for ; Wed, 10 Jan 2024 19:05:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CD99E3858D38 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org CD99E3858D38 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704913551; cv=none; b=vQ32nxzTX+wXUeTLLMDZjFRyN4O1zN9B8XHJEAN+WoA2IgUoR5WjFcpi3YG+ajGg9Nj4R7KJQDOg1B0+u1JYgnNHMnBL5ffeKRI7LYCdOasG4o/hGbWUgwDtu9IRjvuMFoqcXxfwPVhZQ+cT9CQsaE+J+/LnON/LcD/RLtQ+1Bc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704913551; c=relaxed/simple; bh=PafwIp2GM9S4asPbyKvx1K8mfvGc3lEoJM4qhv139Uk=; h=Message-ID:Date:MIME-Version:To:From:Subject; b=k7tIFZFKZ0l/Q9rawgOHg6O1F/NvifZQgpRoL4WIZ8tEw3LTInSLncT1vOXvbZXw3d3rF52W43/mvxiSeo0qBZOXbF5+EcOMVgt8LCCYYjbn8pB+oMXc54Ion9bNEz30EpoQsgzlULNhhyKI4KQLMcgnzyjTACJzGMnY58J8whw= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4AD0D2F4; Wed, 10 Jan 2024 11:06:35 -0800 (PST) Received: from [10.57.76.195] (unknown [10.57.76.195]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DA97E3F64C; Wed, 10 Jan 2024 11:05:47 -0800 (PST) Message-ID: <289f93f5-fe3a-4e04-bd49-390ba7a84a94@arm.com> Date: Wed, 10 Jan 2024 19:05:39 +0000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: "gcc-patches@gcc.gnu.org" Cc: "jakub@redhat.com" From: "Andre Vieira (lists)" Subject: [RFC] aarch64: Add support for __BitInt X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, This patch is still work in progress, but posting to show failure with bitint-7 test where handle_stmt called from lower_mergeable_stmt ICE's because the idx (3) is out of range for the __BitInt(135) with a limb_prec of 64. I hacked gcc locally to work around this issue and still have one outstanding failure, so will look to resolve that failure before posting a new version. Kind Regards, Andre diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index a5a6b52730d6c5013346d128e89915883f1707ae..15fb0ece5256f25c2ca8bb5cb82fc61488d0393e 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -6534,7 +6534,7 @@ aarch64_return_in_memory_1 (const_tree type) machine_mode ag_mode; int count; - if (!AGGREGATE_TYPE_P (type) + if (!(AGGREGATE_TYPE_P (type) || TREE_CODE (type) == BITINT_TYPE) && TREE_CODE (type) != COMPLEX_TYPE && TREE_CODE (type) != VECTOR_TYPE) /* Simple scalar types always returned in registers. */ @@ -6618,6 +6618,10 @@ aarch64_function_arg_alignment (machine_mode mode, const_tree type, gcc_assert (TYPE_MODE (type) == mode); + if (TREE_CODE (type) == BITINT_TYPE + && int_size_in_bytes (type) > 16) + return GET_MODE_ALIGNMENT (TImode); + if (!AGGREGATE_TYPE_P (type)) { /* The ABI alignment is the natural alignment of the type, without @@ -21773,6 +21777,11 @@ aarch64_composite_type_p (const_tree type, if (type && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE)) return true; + if (type + && TREE_CODE (type) == BITINT_TYPE + && int_size_in_bytes (type) > 16) + return true; + if (mode == BLKmode || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT) @@ -28265,6 +28274,29 @@ aarch64_excess_precision (enum excess_precision_type type) return FLT_EVAL_METHOD_UNPREDICTABLE; } +/* Implement TARGET_C_BITINT_TYPE_INFO. + Return true if _BitInt(N) is supported and fill its details into *INFO. */ +bool +aarch64_bitint_type_info (int n, struct bitint_info *info) +{ + if (n <= 8) + info->limb_mode = QImode; + else if (n <= 16) + info->limb_mode = HImode; + else if (n <= 32) + info->limb_mode = SImode; + else + info->limb_mode = DImode; + + if (n > 128) + info->abi_limb_mode = TImode; + else + info->abi_limb_mode = info->limb_mode; + info->big_endian = TARGET_BIG_END; + info->extended = false; + return true; +} + /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be scheduled for speculative execution. Reject the long-running division and square-root instructions. */ @@ -30374,6 +30406,9 @@ aarch64_run_selftests (void) #undef TARGET_C_EXCESS_PRECISION #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision +#undef TARGET_C_BITINT_TYPE_INFO +#define TARGET_C_BITINT_TYPE_INFO aarch64_bitint_type_info + #undef TARGET_EXPAND_BUILTIN #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin diff --git a/libgcc/config/aarch64/t-softfp b/libgcc/config/aarch64/t-softfp index 2e32366f891361e2056c680b2e36edb1871c7670..4302ad52eb881825d0fb65b9ebd21031781781f5 100644 --- a/libgcc/config/aarch64/t-softfp +++ b/libgcc/config/aarch64/t-softfp @@ -4,7 +4,8 @@ softfp_extensions := sftf dftf hftf bfsf softfp_truncations := tfsf tfdf tfhf tfbf dfbf sfbf hfbf softfp_exclude_libgcc2 := n softfp_extras += fixhfti fixunshfti floattihf floatuntihf \ - floatdibf floatundibf floattibf floatuntibf + floatdibf floatundibf floattibf floatuntibf \ + fixtfbitint floatbitinttf TARGET_LIBGCC2_CFLAGS += -Wno-missing-prototypes