Message ID | 2618b501-35e5-4ea2-9425-245dd0df0b3c@linux.ibm.com |
---|---|
State | New |
Headers | show |
Series | [01/11] rs6000, Fix __builtin_vsx_cmple* args and documentation, builtins | expand |
Hi Carl, on 2024/2/21 01:57, Carl Love wrote: > GCC maintainers: > > The patch adds documentation and test case for the __builtin_vsx_xxpermdi_1ti built-in. > > The patch has been tested on Power 10 with no regressions. > > Please let me know if this patch is acceptable for mainline. Thanks. > > Carl > ------------------------------------------------------------ > > rs6000, __builtin_vsx_xxpermdi_1ti add documentation and test case > > Add documentation to the extend.texi file for the > __builtin_vsx_xxpermdi_1ti built-in. I think this one should be part of vec_xxpermdi (overload.def), we can extend vec_xxpermdi by one more instance with type vsq, also update the documentation on vec_xxpermdi for this newly introduced. BR, Kewen > > Add test cases for the __builtin_vsx_xxpermdi_1ti built-in. > > gcc/ChangeLog: > * doc/extend.texi (__builtin_vsx_xxpermdi_1ti): Add documentation. > > gcc/testsuite/ChangeLog: > * gcc.target/powerpc/vsx-builtin-runnable-3.c: New test case. > --- > gcc/doc/extend.texi | 7 +++ > .../powerpc/vsx-builtin-runnable-3.c | 48 +++++++++++++++++++ > 2 files changed, 55 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-3.c > > diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi > index 83eed9e334b..22f67ebab31 100644 > --- a/gcc/doc/extend.texi > +++ b/gcc/doc/extend.texi > @@ -21508,6 +21508,13 @@ vector __int128 __builtin_vsx_xxpermdi_1ti (vector __int128, vector __int128, > const int); > > @end smallexample > + > +The @code{__builtin_vsx_xxpermdi_1ti} Let srcA[127:0] be the 128-bit first > +argument and srcB[127:0] be the 128-bit second argument. Let sel[1:0] be the > +least significant bits of the const int argument (third input argument). The > +result bits [127:64] is srcB[127:64] if sel[1] = 0, srcB[63:0] otherwise. The > +result bits [63:0] is srcA[127:64] if sel[0] = 0, srcA[63:0] otherwise. > + > @node Basic PowerPC Built-in Functions Available on ISA 2.07 > @subsubsection Basic PowerPC Built-in Functions Available on ISA 2.07 > > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-3.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-3.c > new file mode 100644 > index 00000000000..ba287597cec > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-3.c > @@ -0,0 +1,48 @@ > +/* { dg-do run { target { lp64 } } } */ > +/* { dg-require-effective-target powerpc_vsx_ok } */ > +/* { dg-options "-O2 -mdejagnu-cpu=power7" } */ > + > +#include <altivec.h> > + > +#define DEBUG 0 > + > +#if DEBUG > +#include <stdio.h> > +#include <stdlib.h> > +#endif > + > +void abort (void); > + > +int main () > +{ > + int i; > + > + vector signed __int128 vsq_arg1, vsq_arg2, vsq_result, vsq_expected_result; > + > + vsq_arg1[0] = (__int128) 0xFFFF0000FFFF0000; > + vsq_arg1[0] = vsq_arg1[0] << 64 | (__int128) 0xFFFF0000FFFF; > + vsq_arg2[0] = (__int128) 0x1100110011001100; > + vsq_arg2[0] = (vsq_arg2[0] << 64) | (__int128) 0x1111000011110000; > + > + vsq_expected_result[0] = (__int128) 0x1111000011110000; > + vsq_expected_result[0] = (vsq_expected_result[0] << 64) > + | (__int128) 0xFFFF0000FFFF0000; > + > + vsq_result = __builtin_vsx_xxpermdi_1ti (vsq_arg1, vsq_arg2, 2); > + > + if (vsq_result[0] != vsq_expected_result[0]) > + { > +#if DEBUG > + printf("ERROR, __builtin_vsx_xxpermdi_1ti: vsq_result = 0x%016llx %016llx\n", > + (unsigned long long) (vsq_result[0] >> 64), > + (unsigned long long) vsq_result[0]); > + printf(" vsq_expected_resultd = 0x%016llx %016llx\n", > + (unsigned long long)(vsq_expected_result[0] >> 64), > + (unsigned long long) vsq_expected_result[0]); > +#else > + abort(); > +#endif > + } > + > + return 0; > +}
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 83eed9e334b..22f67ebab31 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -21508,6 +21508,13 @@ vector __int128 __builtin_vsx_xxpermdi_1ti (vector __int128, vector __int128, const int); @end smallexample + +The @code{__builtin_vsx_xxpermdi_1ti} Let srcA[127:0] be the 128-bit first +argument and srcB[127:0] be the 128-bit second argument. Let sel[1:0] be the +least significant bits of the const int argument (third input argument). The +result bits [127:64] is srcB[127:64] if sel[1] = 0, srcB[63:0] otherwise. The +result bits [63:0] is srcA[127:64] if sel[0] = 0, srcA[63:0] otherwise. + @node Basic PowerPC Built-in Functions Available on ISA 2.07 @subsubsection Basic PowerPC Built-in Functions Available on ISA 2.07 diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-3.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-3.c new file mode 100644 index 00000000000..ba287597cec --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-3.c @@ -0,0 +1,48 @@ +/* { dg-do run { target { lp64 } } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power7" } */ + +#include <altivec.h> + +#define DEBUG 0 + +#if DEBUG +#include <stdio.h> +#include <stdlib.h> +#endif + +void abort (void); + +int main () +{ + int i; + + vector signed __int128 vsq_arg1, vsq_arg2, vsq_result, vsq_expected_result; + + vsq_arg1[0] = (__int128) 0xFFFF0000FFFF0000; + vsq_arg1[0] = vsq_arg1[0] << 64 | (__int128) 0xFFFF0000FFFF; + vsq_arg2[0] = (__int128) 0x1100110011001100; + vsq_arg2[0] = (vsq_arg2[0] << 64) | (__int128) 0x1111000011110000; + + vsq_expected_result[0] = (__int128) 0x1111000011110000; + vsq_expected_result[0] = (vsq_expected_result[0] << 64) + | (__int128) 0xFFFF0000FFFF0000; + + vsq_result = __builtin_vsx_xxpermdi_1ti (vsq_arg1, vsq_arg2, 2); + + if (vsq_result[0] != vsq_expected_result[0]) + { +#if DEBUG + printf("ERROR, __builtin_vsx_xxpermdi_1ti: vsq_result = 0x%016llx %016llx\n", + (unsigned long long) (vsq_result[0] >> 64), + (unsigned long long) vsq_result[0]); + printf(" vsq_expected_resultd = 0x%016llx %016llx\n", + (unsigned long long)(vsq_expected_result[0] >> 64), + (unsigned long long) vsq_expected_result[0]); +#else + abort(); +#endif + } + + return 0; +}