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Sun, 14 Jan 2024 06:56:12 -0800 (PST) Message-ID: <24325532-9484-4f9f-adb3-59d206505d9d@gmail.com> Date: Sun, 14 Jan 2024 07:56:10 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US From: Jeff Law To: "gcc-patches@gcc.gnu.org" Subject: [committed] Fix MIPS bootstrap X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org mips bootstraps have been broken for a while. They've been triggering an error about mutually exclusive equal-tests always being false when building gencondmd. This was ultimately tracked down to the ior3_mips16_asmacro pattern. The pattern uses the GPR mode iterator which looks like this: (define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) The condition for the pattern looks like this: "ISA_HAS_MIPS16E2" And if you dig into ISA_HAS_MIPS16E2: /* The MIPS16e V2 instructions are available. */ #define ISA_HAS_MIPS16E2 (TARGET_MIPS16 && TARGET_MIPS16E2 \ && !TARGET_64BIT) The way the mode iterator is handled is by adding its condition to the pattern's condition when we expand copies of the pattern resulting in this condition for one of the two generated patterns: (TARGET_MIPS16 && TARGET_MIPS16E2 && !TARGET_64BIT) && TARGET_64BIT This can never be true because of the TARGET_64BIT tests. The fix is trivial. Don't use a mode iterator on that pattern. Bootstrapped on mips64el. I don't have any tests to compare against, so no regression test data. Pushed to the trunk, Jeff commit e927cfa842c16bea902500e69ab4eca2ef15af4e Author: Jeff Law Date: Sun Jan 14 07:53:49 2024 -0700 [committed] Fix MIPS bootstrap mips bootstraps have been broken for a while. They've been triggering an error about mutually exclusive equal-tests always being false when building gencondmd. This was ultimately tracked down to the ior3_mips16_asmacro pattern. The pattern uses the GPR mode iterator which looks like this: (define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) The condition for the pattern looks like this: "ISA_HAS_MIPS16E2" And if you dig into ISA_HAS_MIPS16E2: /* The MIPS16e V2 instructions are available. */ && !TARGET_64BIT) The way the mode iterator is handled is by adding its condition to the pattern's condition when we expand copies of the pattern resulting in this condition for one of the two generated patterns: (TARGET_MIPS16 && TARGET_MIPS16E2 && !TARGET_64BIT) && TARGET_64BIT This can never be true because of the TARGET_64BIT tests. The fix is trivial. Don't use a mode iterator on that pattern. Bootstrapped on mips64el. I don't have any tests to compare against, so no regression test data. gcc/ * config/mips/mips.md (ior3_mips16_asmacro): Use SImode, not the GPR iterator. Adjust pattern name and mode attribute accordingly. diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 17dfcbd6722..b0fb5850a9e 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -3440,16 +3440,16 @@ (define_insn "*ior3" (set_attr "compression" "micromips,*,*") (set_attr "mode" "")]) -(define_insn "*ior3_mips16_asmacro" - [(set (match_operand:GPR 0 "register_operand" "=d,d") - (ior:GPR (match_operand:GPR 1 "register_operand" "%0,0") - (match_operand:GPR 2 "uns_arith_operand" "d,K")))] +(define_insn "*iorsi3_mips16_asmacro" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (ior:SI (match_operand:SI 1 "register_operand" "%0,0") + (match_operand:SI 2 "uns_arith_operand" "d,K")))] "ISA_HAS_MIPS16E2" "@ or\t%0,%2 ori\t%0,%x2" [(set_attr "alu_type" "or") - (set_attr "mode" "") + (set_attr "mode" "SI") (set_attr "extended_mips16" "*,yes")]) (define_insn "*ior3_mips16"