| Message ID | 23e691f7-8a72-4a1a-9b20-aab5a31b9a96@linux.ibm.com |
|---|---|
| State | New |
| Headers | show |
| Series | [PATCH-1v4,rs6000] Implement optab_isinf for SFDF and IEEE128 | expand |
Hi Haochen, on 2024/6/27 09:41, HAO CHEN GUI wrote: > Hi, > This patch implemented optab_isinf for SFDF and IEEE128 by test > data class instructions. > > Compared with previous version, the main change is to define > and use the constant mask for test data class insns. > https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652593.html > > Bootstrapped and tested on powerpc64-linux BE and LE with no > regressions. Is it OK for trunk? > > Thanks > Gui Haochen > > ChangeLog > rs6000: Implement optab_isinf for SFDF and IEEE128 > > gcc/ > PR target/97786 > * config/rs6000/rs6000.md (ISNAN, ISINF, ISZERO, ISDENORMAL): Define. > * config/rs6000/vsx.md (isinf<mode>2 for SFDF): New expand. > (isinf<mode>2 for IEEE128): New expand. > > gcc/testsuite/ > PR target/97786 > * gcc.target/powerpc/pr97786-1.c: New test. > * gcc.target/powerpc/pr97786-2.c: New test. > > patch.diff > diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md > index ac5651d7420..e84e6b08f03 100644 > --- a/gcc/config/rs6000/rs6000.md > +++ b/gcc/config/rs6000/rs6000.md > @@ -53,6 +53,17 @@ (define_constants > (FRAME_POINTER_REGNUM 110) > ]) > > +;; > +;; Test data class mask > +;; > + > +(define_constants > + [(ISNAN 0x40) > + (ISINF 0x30) > + (ISZERO 0xC) > + (ISDENORMAL 0x3) Nit: Maybe it's better to add prefix on test data class, such as: TEST_DATA_CLASS_NAN or DATA_CLASS_NAN. And DATA_CLASS_INF can be separated as DATA_CLASS_POS_INF 0x20 and DATA_CLASS_NEG_INF 0x10, similar separating for DENORM. > + ]) > + > ;; > ;; UNSPEC usage > ;; > diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md > index f135fa079bd..67615bae8c0 100644 > --- a/gcc/config/rs6000/vsx.md > +++ b/gcc/config/rs6000/vsx.md > @@ -5313,6 +5313,24 @@ (define_expand "xststdc<sd>p" > operands[4] = CONST0_RTX (SImode); > }) > > +(define_expand "isinf<mode>2" > + [(use (match_operand:SI 0 "gpc_reg_operand")) > + (use (match_operand:SFDF 1 "vsx_register_operand"))] > + "TARGET_HARD_FLOAT && TARGET_P9_VECTOR" > +{ > + emit_insn (gen_xststdc<sd>p (operands[0], operands[1], GEN_INT (ISINF))); > + DONE; > +}) > + > +(define_expand "isinf<mode>2" > + [(use (match_operand:SI 0 "gpc_reg_operand")) > + (use (match_operand:IEEE128 1 "vsx_register_operand"))] QP insns are special, only altivec regs can be used, so s/vsx_register_operand/altivec_register_operand/ Also applied to the other two patches for isnormal and isfinite. And as discussed offline, let's merge these patterns with mode attribute. :) > + "TARGET_HARD_FLOAT && TARGET_P9_VECTOR" > +{ > + emit_insn (gen_xststdcqp_<mode> (operands[0], operands[1], GEN_INT (ISINF))); > + DONE; > +}) > + > ;; The VSX Scalar Test Negative Quad-Precision > (define_expand "xststdcnegqp_<mode>" > [(set (match_dup 2) > diff --git a/gcc/testsuite/gcc.target/powerpc/pr97786-1.c b/gcc/testsuite/gcc.target/powerpc/pr97786-1.c > new file mode 100644 > index 00000000000..c1c4f64ee8b > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr97786-1.c > @@ -0,0 +1,22 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target powerpc_vsx } */ > +/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ Nit: Not necessary, but it's preferred to put dg-options line before the line for powerpc_vsx as powerpc_vsx considers current_compiler_flags but dg-options line isn't processed if it's put behind. Also applied for the other test cases. BR, Kewen > + > +int test1 (double x) > +{ > + return __builtin_isinf (x); > +} > + > +int test2 (float x) > +{ > + return __builtin_isinf (x); > +} > + > +int test3 (float x) > +{ > + return __builtin_isinff (x); > +} > + > +/* { dg-final { scan-assembler-not {\mfcmp} } } */ > +/* { dg-final { scan-assembler-times {\mxststdcsp\M} 2 } } */ > +/* { dg-final { scan-assembler-times {\mxststdcdp\M} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/powerpc/pr97786-2.c b/gcc/testsuite/gcc.target/powerpc/pr97786-2.c > new file mode 100644 > index 00000000000..ed305e8572e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr97786-2.c > @@ -0,0 +1,17 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target ppc_float128_hw } */ > +/* { dg-require-effective-target powerpc_vsx } */ > +/* { dg-options "-O2 -mdejagnu-cpu=power9 -mabi=ieeelongdouble -Wno-psabi" } */ > + > +int test1 (long double x) > +{ > + return __builtin_isinf (x); > +} > + > +int test2 (long double x) > +{ > + return __builtin_isinfl (x); > +} > + > +/* { dg-final { scan-assembler-not {\mxscmpuqp\M} } } */ > +/* { dg-final { scan-assembler-times {\mxststdcqp\M} 2 } } */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index ac5651d7420..e84e6b08f03 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -53,6 +53,17 @@ (define_constants (FRAME_POINTER_REGNUM 110) ]) +;; +;; Test data class mask +;; + +(define_constants + [(ISNAN 0x40) + (ISINF 0x30) + (ISZERO 0xC) + (ISDENORMAL 0x3) + ]) + ;; ;; UNSPEC usage ;; diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index f135fa079bd..67615bae8c0 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5313,6 +5313,24 @@ (define_expand "xststdc<sd>p" operands[4] = CONST0_RTX (SImode); }) +(define_expand "isinf<mode>2" + [(use (match_operand:SI 0 "gpc_reg_operand")) + (use (match_operand:SFDF 1 "vsx_register_operand"))] + "TARGET_HARD_FLOAT && TARGET_P9_VECTOR" +{ + emit_insn (gen_xststdc<sd>p (operands[0], operands[1], GEN_INT (ISINF))); + DONE; +}) + +(define_expand "isinf<mode>2" + [(use (match_operand:SI 0 "gpc_reg_operand")) + (use (match_operand:IEEE128 1 "vsx_register_operand"))] + "TARGET_HARD_FLOAT && TARGET_P9_VECTOR" +{ + emit_insn (gen_xststdcqp_<mode> (operands[0], operands[1], GEN_INT (ISINF))); + DONE; +}) + ;; The VSX Scalar Test Negative Quad-Precision (define_expand "xststdcnegqp_<mode>" [(set (match_dup 2) diff --git a/gcc/testsuite/gcc.target/powerpc/pr97786-1.c b/gcc/testsuite/gcc.target/powerpc/pr97786-1.c new file mode 100644 index 00000000000..c1c4f64ee8b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr97786-1.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ + +int test1 (double x) +{ + return __builtin_isinf (x); +} + +int test2 (float x) +{ + return __builtin_isinf (x); +} + +int test3 (float x) +{ + return __builtin_isinff (x); +} + +/* { dg-final { scan-assembler-not {\mfcmp} } } */ +/* { dg-final { scan-assembler-times {\mxststdcsp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxststdcdp\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr97786-2.c b/gcc/testsuite/gcc.target/powerpc/pr97786-2.c new file mode 100644 index 00000000000..ed305e8572e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr97786-2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ppc_float128_hw } */ +/* { dg-require-effective-target powerpc_vsx } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9 -mabi=ieeelongdouble -Wno-psabi" } */ + +int test1 (long double x) +{ + return __builtin_isinf (x); +} + +int test2 (long double x) +{ + return __builtin_isinfl (x); +} + +/* { dg-final { scan-assembler-not {\mxscmpuqp\M} } } */ +/* { dg-final { scan-assembler-times {\mxststdcqp\M} 2 } } */