| Message ID | 23187440-ee81-4816-b3be-2682e64912ed@linux.ibm.com |
|---|---|
| State | New |
| Headers | show |
| Series | [PATCHv2,rs6000] Add TARGET_FLOAT128_HW guard for quad-precision insns | expand |
Hi Haochen, on 2024/7/15 10:10, HAO CHEN GUI wrote: > Hi, > This patch adds TARGET_FLOAT128_HW into pattern conditions for quad- > precision insns. Some qp patterns are guarded by TARGET_P9_VECTOR > originally, so replace it with "TARGET_FLOAT128_HW". > > For test case float128-cmp2-runnable.c, it should be guarded with > ppc_float128_hw as it calls qp insns. The p9vector_hw is covered with > ppc_float128_hw, so it's removed. > > Compared to previous version, the main change it to split redundant > FLOAT128_IEEE_P removal to another patch. > > Bootstrapped and tested on powerpc64-linux BE and LE with no > regressions. Is it OK for trunk? OK for trunk, thanks! BR, Kewen > > Thanks > Gui Haochen > > ChangeLog > rs6000: Add TARGET_FLOAT128_HW guard for quad-precision insns > > gcc/ > * config/rs6000/rs6000.md (floatti<mode>2, floatunsti<mode>2, > fix_trunc<mode>ti2): Add guard TARGET_FLOAT128_HW. > * config/rs6000/vsx.md (xsxexpqp_<IEEE128:mode>_<V2DI_DI:mode>, > xsxsigqp_<IEEE128:mode>_<VEC_TI:mode>, xsiexpqpf_<mode>, > xsiexpqp_<IEEE128:mode>_<V2DI_DI:mode>, xscmpexpqp_<code>_<mode>, > *xscmpexpqp, xststdcnegqp_<mode>): Replace guard TARGET_P9_VECTOR > with TARGET_FLOAT128_HW. > (xststdc_<mode>, *xststdc_<mode>, isinf<mode>2): Add guard > TARGET_FLOAT128_HW for the IEEE128 modes. > > gcc/testsuite/ > * testsuite/gcc.target/powerpc/float128-cmp2-runnable.c: Replace > ppc_float128_sw with ppc_float128_hw and remove p9vector_hw. > > patch.diff > diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md > index deffc4b601c..c0f6599c08b 100644 > --- a/gcc/config/rs6000/rs6000.md > +++ b/gcc/config/rs6000/rs6000.md > @@ -6928,7 +6928,7 @@ (define_insn "floatdidf2" > (define_insn "floatti<mode>2" > [(set (match_operand:IEEE128 0 "vsx_register_operand" "=v") > (float:IEEE128 (match_operand:TI 1 "vsx_register_operand" "v")))] > - "TARGET_POWER10" > + "TARGET_POWER10 && TARGET_FLOAT128_HW" > { > return "xscvsqqp %0,%1"; > } > @@ -6937,7 +6937,7 @@ (define_insn "floatti<mode>2" > (define_insn "floatunsti<mode>2" > [(set (match_operand:IEEE128 0 "vsx_register_operand" "=v") > (unsigned_float:IEEE128 (match_operand:TI 1 "vsx_register_operand" "v")))] > - "TARGET_POWER10" > + "TARGET_POWER10 && TARGET_FLOAT128_HW" > { > return "xscvuqqp %0,%1"; > } > @@ -6946,7 +6946,7 @@ (define_insn "floatunsti<mode>2" > (define_insn "fix_trunc<mode>ti2" > [(set (match_operand:TI 0 "vsx_register_operand" "=v") > (fix:TI (match_operand:IEEE128 1 "vsx_register_operand" "v")))] > - "TARGET_POWER10" > + "TARGET_POWER10 && TARGET_FLOAT128_HW" > { > return "xscvqpsqz %0,%1"; > } > diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md > index 1272f8b2080..7dd08895bec 100644 > --- a/gcc/config/rs6000/vsx.md > +++ b/gcc/config/rs6000/vsx.md > @@ -5157,7 +5157,7 @@ (define_insn "xsxexpqp_<IEEE128:mode>_<V2DI_DI:mode>" > (unspec:V2DI_DI > [(match_operand:IEEE128 1 "altivec_register_operand" "v")] > UNSPEC_VSX_SXEXPDP))] > - "TARGET_P9_VECTOR" > + "TARGET_FLOAT128_HW" > "xsxexpqp %0,%1" > [(set_attr "type" "vecmove")]) > > @@ -5176,7 +5176,7 @@ (define_insn "xsxsigqp_<IEEE128:mode>_<VEC_TI:mode>" > (unspec:VEC_TI [(match_operand:IEEE128 1 > "altivec_register_operand" "v")] > UNSPEC_VSX_SXSIG))] > - "TARGET_P9_VECTOR" > + "TARGET_FLOAT128_HW" > "xsxsigqp %0,%1" > [(set_attr "type" "vecmove")]) > > @@ -5196,7 +5196,7 @@ (define_insn "xsiexpqpf_<mode>" > [(match_operand:IEEE128 1 "altivec_register_operand" "v") > (match_operand:DI 2 "altivec_register_operand" "v")] > UNSPEC_VSX_SIEXPQP))] > - "TARGET_P9_VECTOR" > + "TARGET_FLOAT128_HW" > "xsiexpqp %0,%1,%2" > [(set_attr "type" "vecmove")]) > > @@ -5208,7 +5208,7 @@ (define_insn "xsiexpqp_<IEEE128:mode>_<V2DI_DI:mode>" > (match_operand:V2DI_DI 2 > "altivec_register_operand" "v")] > UNSPEC_VSX_SIEXPQP))] > - "TARGET_P9_VECTOR" > + "TARGET_FLOAT128_HW" > "xsiexpqp %0,%1,%2" > [(set_attr "type" "vecmove")]) > > @@ -5278,7 +5278,7 @@ (define_expand "xscmpexpqp_<code>_<mode>" > (set (match_operand:SI 0 "register_operand" "=r") > (CMP_TEST:SI (match_dup 3) > (const_int 0)))] > - "TARGET_P9_VECTOR" > + "TARGET_FLOAT128_HW" > { > if (<CODE> == UNORDERED && !HONOR_NANS (<MODE>mode)) > { > @@ -5296,7 +5296,7 @@ (define_insn "*xscmpexpqp" > (match_operand:IEEE128 2 "altivec_register_operand" "v")] > UNSPEC_VSX_SCMPEXPQP) > (match_operand:SI 3 "zero_constant" "j")))] > - "TARGET_P9_VECTOR" > + "TARGET_FLOAT128_HW" > "xscmpexpqp %0,%1,%2" > [(set_attr "type" "fpcompare")]) > > @@ -5315,7 +5315,8 @@ (define_expand "xststdc_<mode>" > (set (match_operand:SI 0 "register_operand" "=r") > (eq:SI (match_dup 3) > (const_int 0)))] > - "TARGET_P9_VECTOR" > + "TARGET_P9_VECTOR > + && (!FLOAT128_IEEE_P (<MODE>mode) || TARGET_FLOAT128_HW)" > { > operands[3] = gen_reg_rtx (CCFPmode); > operands[4] = CONST0_RTX (SImode); > @@ -5324,7 +5325,8 @@ (define_expand "xststdc_<mode>" > (define_expand "isinf<mode>2" > [(use (match_operand:SI 0 "gpc_reg_operand")) > (use (match_operand:IEEE_FP 1 "<fp_register_op>"))] > - "TARGET_HARD_FLOAT && TARGET_P9_VECTOR" > + "TARGET_P9_VECTOR > + && (!FLOAT128_IEEE_P (<MODE>mode) || TARGET_FLOAT128_HW)" > { > int mask = VSX_TEST_DATA_CLASS_POS_INF | VSX_TEST_DATA_CLASS_NEG_INF; > emit_insn (gen_xststdc_<mode> (operands[0], operands[1], GEN_INT (mask))); > @@ -5343,7 +5345,7 @@ (define_expand "xststdcnegqp_<mode>" > (set (match_operand:SI 0 "register_operand" "=r") > (lt:SI (match_dup 2) > (const_int 0)))] > - "TARGET_P9_VECTOR" > + "TARGET_FLOAT128_HW" > { > operands[2] = gen_reg_rtx (CCFPmode); > }) > @@ -5374,7 +5376,8 @@ (define_insn "*xststdc_<mode>" > (match_operand:SI 2 "u7bit_cint_operand" "n")] > UNSPEC_VSX_STSTDC) > (const_int 0)))] > - "TARGET_P9_VECTOR" > + "TARGET_P9_VECTOR > + && (!FLOAT128_IEEE_P (<MODE>mode) || TARGET_FLOAT128_HW)" > "xststdc<sdq>p %0,%<x>1,%2" > [(set_attr "type" "fpcompare")]) > > diff --git a/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c b/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c > index d376a3ca68e..f48aa089b05 100644 > --- a/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c > +++ b/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c > @@ -1,6 +1,5 @@ > /* { dg-do run } */ > -/* { dg-require-effective-target ppc_float128_sw } */ > -/* { dg-require-effective-target p9vector_hw } */ > +/* { dg-require-effective-target ppc_float128_hw } */ > /* { dg-options "-O2 -mdejagnu-cpu=power9 " } */ > > #define NAN_Q __builtin_nanq ("")
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index deffc4b601c..c0f6599c08b 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -6928,7 +6928,7 @@ (define_insn "floatdidf2" (define_insn "floatti<mode>2" [(set (match_operand:IEEE128 0 "vsx_register_operand" "=v") (float:IEEE128 (match_operand:TI 1 "vsx_register_operand" "v")))] - "TARGET_POWER10" + "TARGET_POWER10 && TARGET_FLOAT128_HW" { return "xscvsqqp %0,%1"; } @@ -6937,7 +6937,7 @@ (define_insn "floatti<mode>2" (define_insn "floatunsti<mode>2" [(set (match_operand:IEEE128 0 "vsx_register_operand" "=v") (unsigned_float:IEEE128 (match_operand:TI 1 "vsx_register_operand" "v")))] - "TARGET_POWER10" + "TARGET_POWER10 && TARGET_FLOAT128_HW" { return "xscvuqqp %0,%1"; } @@ -6946,7 +6946,7 @@ (define_insn "floatunsti<mode>2" (define_insn "fix_trunc<mode>ti2" [(set (match_operand:TI 0 "vsx_register_operand" "=v") (fix:TI (match_operand:IEEE128 1 "vsx_register_operand" "v")))] - "TARGET_POWER10" + "TARGET_POWER10 && TARGET_FLOAT128_HW" { return "xscvqpsqz %0,%1"; } diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 1272f8b2080..7dd08895bec 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5157,7 +5157,7 @@ (define_insn "xsxexpqp_<IEEE128:mode>_<V2DI_DI:mode>" (unspec:V2DI_DI [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_VSX_SXEXPDP))] - "TARGET_P9_VECTOR" + "TARGET_FLOAT128_HW" "xsxexpqp %0,%1" [(set_attr "type" "vecmove")]) @@ -5176,7 +5176,7 @@ (define_insn "xsxsigqp_<IEEE128:mode>_<VEC_TI:mode>" (unspec:VEC_TI [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_VSX_SXSIG))] - "TARGET_P9_VECTOR" + "TARGET_FLOAT128_HW" "xsxsigqp %0,%1" [(set_attr "type" "vecmove")]) @@ -5196,7 +5196,7 @@ (define_insn "xsiexpqpf_<mode>" [(match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:DI 2 "altivec_register_operand" "v")] UNSPEC_VSX_SIEXPQP))] - "TARGET_P9_VECTOR" + "TARGET_FLOAT128_HW" "xsiexpqp %0,%1,%2" [(set_attr "type" "vecmove")]) @@ -5208,7 +5208,7 @@ (define_insn "xsiexpqp_<IEEE128:mode>_<V2DI_DI:mode>" (match_operand:V2DI_DI 2 "altivec_register_operand" "v")] UNSPEC_VSX_SIEXPQP))] - "TARGET_P9_VECTOR" + "TARGET_FLOAT128_HW" "xsiexpqp %0,%1,%2" [(set_attr "type" "vecmove")]) @@ -5278,7 +5278,7 @@ (define_expand "xscmpexpqp_<code>_<mode>" (set (match_operand:SI 0 "register_operand" "=r") (CMP_TEST:SI (match_dup 3) (const_int 0)))] - "TARGET_P9_VECTOR" + "TARGET_FLOAT128_HW" { if (<CODE> == UNORDERED && !HONOR_NANS (<MODE>mode)) { @@ -5296,7 +5296,7 @@ (define_insn "*xscmpexpqp" (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_VSX_SCMPEXPQP) (match_operand:SI 3 "zero_constant" "j")))] - "TARGET_P9_VECTOR" + "TARGET_FLOAT128_HW" "xscmpexpqp %0,%1,%2" [(set_attr "type" "fpcompare")]) @@ -5315,7 +5315,8 @@ (define_expand "xststdc_<mode>" (set (match_operand:SI 0 "register_operand" "=r") (eq:SI (match_dup 3) (const_int 0)))] - "TARGET_P9_VECTOR" + "TARGET_P9_VECTOR + && (!FLOAT128_IEEE_P (<MODE>mode) || TARGET_FLOAT128_HW)" { operands[3] = gen_reg_rtx (CCFPmode); operands[4] = CONST0_RTX (SImode); @@ -5324,7 +5325,8 @@ (define_expand "xststdc_<mode>" (define_expand "isinf<mode>2" [(use (match_operand:SI 0 "gpc_reg_operand")) (use (match_operand:IEEE_FP 1 "<fp_register_op>"))] - "TARGET_HARD_FLOAT && TARGET_P9_VECTOR" + "TARGET_P9_VECTOR + && (!FLOAT128_IEEE_P (<MODE>mode) || TARGET_FLOAT128_HW)" { int mask = VSX_TEST_DATA_CLASS_POS_INF | VSX_TEST_DATA_CLASS_NEG_INF; emit_insn (gen_xststdc_<mode> (operands[0], operands[1], GEN_INT (mask))); @@ -5343,7 +5345,7 @@ (define_expand "xststdcnegqp_<mode>" (set (match_operand:SI 0 "register_operand" "=r") (lt:SI (match_dup 2) (const_int 0)))] - "TARGET_P9_VECTOR" + "TARGET_FLOAT128_HW" { operands[2] = gen_reg_rtx (CCFPmode); }) @@ -5374,7 +5376,8 @@ (define_insn "*xststdc_<mode>" (match_operand:SI 2 "u7bit_cint_operand" "n")] UNSPEC_VSX_STSTDC) (const_int 0)))] - "TARGET_P9_VECTOR" + "TARGET_P9_VECTOR + && (!FLOAT128_IEEE_P (<MODE>mode) || TARGET_FLOAT128_HW)" "xststdc<sdq>p %0,%<x>1,%2" [(set_attr "type" "fpcompare")]) diff --git a/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c b/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c index d376a3ca68e..f48aa089b05 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c @@ -1,6 +1,5 @@ /* { dg-do run } */ -/* { dg-require-effective-target ppc_float128_sw } */ -/* { dg-require-effective-target p9vector_hw } */ +/* { dg-require-effective-target ppc_float128_hw } */ /* { dg-options "-O2 -mdejagnu-cpu=power9 " } */ #define NAN_Q __builtin_nanq ("")