From patchwork Fri Oct 22 19:56:02 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Koning X-Patchwork-Id: 68949 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 809BEB6EF0 for ; Sat, 23 Oct 2010 06:56:57 +1100 (EST) Received: (qmail 24053 invoked by alias); 22 Oct 2010 19:56:52 -0000 Received: (qmail 24034 invoked by uid 22791); 22 Oct 2010 19:56:51 -0000 X-SWARE-Spam-Status: No, hits=-1.7 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from ausc60pc101.us.dell.com (HELO ausc60pc101.us.dell.com) (143.166.85.206) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 22 Oct 2010 19:56:45 +0000 X-Loopcount0: from 10.152.240.141 From: Paul Koning Subject: [PATCH] pdp11: add IRA_COVER_CLASSES Date: Fri, 22 Oct 2010 15:56:02 -0400 Message-Id: <22F1FB4D-B446-467E-B9A0-F5AA5369E383@dell.com> To: gcc-patches Mime-Version: 1.0 (Apple Message framework v1081) Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org This patch defines IRA_COVER_CLASSES for pdp11. Tested by cross build and check on compile testcases. The testcase results change slightly; I'm planning to dig into that later. Committed. paul ChangeLog: 2010-10-22 Paul Koning * config/pdp11/pdp11.h (IRA_COVER_CLASSES): Define. Index: config/pdp11/pdp11.h =================================================================== --- config/pdp11/pdp11.h (revision 165842) +++ config/pdp11/pdp11.h (working copy) @@ -320,6 +320,16 @@ #define INDEX_REG_CLASS GENERAL_REGS #define BASE_REG_CLASS GENERAL_REGS +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ + +#define IRA_COVER_CLASSES { GENERAL_REGS, FPU_REGS, LIM_REG_CLASSES } + /* Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines