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[46.5.130.86]) by smtp.gmail.com with ESMTPSA id w23-20020aa7cb57000000b0050b57848b01sm2739619edt.82.2023.05.11.03.33.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 May 2023 03:33:51 -0700 (PDT) Message-ID: <22063fee-8e38-6da4-8658-4e7c80a3199e@gmail.com> Date: Thu, 11 May 2023 12:33:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: [PATCH v2] RISC-V: Split off shift patterns for autovectorization. Content-Language: en-US To: Palmer Dabbelt Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai, Kito Cheng , collison@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com References: In-Reply-To: X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Robin Dapp via Gcc-patches From: Robin Dapp Reply-To: Robin Dapp Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" > "csr_operand" does seem wrong, though, as that just accepts constants. > Maybe "arith_operand" is the way to go? I haven't looked at the > V immediates though. I was pondering changing the shift-count operand to QImode everywhere but that indeed does not help code generation across the board. It can still work but might require extra patterns here and there. "csr_operand" accepts 0-31 constants as well as registers which should be fine here. No changes from v1 apart from the RISC-V in the subject and a bit of rebasing and comments. This patch splits off the shift patterns of the binop patterns. This is necessary as the scalar shifts require a Pmode operand as shift count. To this end, a new iterator any_int_binop_no_shift is introduced. At a later point when the binops are split up further in commutative and non-commutative patterns (which both do not include the shift patterns) we might not need this anymore. gcc/ChangeLog: * config/riscv/autovec.md (3): Add scalar shift pattern. (v3): Add vector shift pattern. * config/riscv/vector-iterators.md: New iterator. --- gcc/config/riscv/autovec.md | 47 +++++++++++++++++++++++++++- gcc/config/riscv/vector-iterators.md | 4 +++ 2 files changed, 50 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 58926ed3e67..ac0c939d277 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -97,7 +97,7 @@ (define_expand "@vec_series" (define_expand "3" [(set (match_operand:VI 0 "register_operand") - (any_int_binop:VI + (any_int_binop_no_shift:VI (match_operand:VI 1 "") (match_operand:VI 2 "")))] "TARGET_VECTOR" @@ -119,3 +119,48 @@ (define_expand "3" NULL, mode); DONE; }) + +;; ------------------------------------------------------------------------- +;; ---- [INT] Binary shifts by scalar. +;; ------------------------------------------------------------------------- +;; Includes: +;; - vsll.vx/vsra.vx/vsrl.vx +;; - vsll.vi/vsra.vi/vsrl.vi +;; ------------------------------------------------------------------------- + +(define_expand "3" + [(set (match_operand:VI 0 "register_operand") + (any_shift:VI + (match_operand:VI 1 "register_operand") + (match_operand: 2 "csr_operand")))] + "TARGET_VECTOR" +{ + if (!CONST_SCALAR_INT_P (operands[2])) + operands[2] = gen_lowpart (Pmode, operands[2]); + riscv_vector::emit_len_binop (code_for_pred_scalar + (, mode), + operands[0], operands[1], operands[2], + NULL_RTX, mode, Pmode); + DONE; +}) + +;; ------------------------------------------------------------------------- +;; ---- [INT] Binary shifts by scalar. +;; ------------------------------------------------------------------------- +;; Includes: +;; - vsll.vv/vsra.vv/vsrl.vv +;; ------------------------------------------------------------------------- + +(define_expand "v3" + [(set (match_operand:VI 0 "register_operand") + (any_shift:VI + (match_operand:VI 1 "register_operand") + (match_operand:VI 2 "vector_shift_operand")))] + "TARGET_VECTOR" +{ + riscv_vector::emit_len_binop (code_for_pred + (, mode), + operands[0], operands[1], operands[2], + NULL_RTX, mode); + DONE; +}) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 29c9d77674b..5cf958ba845 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -1409,6 +1409,10 @@ (define_code_iterator any_commutative_binop [plus and ior xor (define_code_iterator any_non_commutative_binop [minus div udiv mod umod]) +(define_code_iterator any_int_binop_no_shift + [plus minus and ior xor smax umax smin umin mult div udiv mod umod +]) + (define_code_iterator any_sat_int_binop [ss_plus ss_minus us_plus us_minus]) (define_code_iterator sat_int_plus_binop [ss_plus us_plus]) (define_code_iterator sat_int_minus_binop [ss_minus us_minus])