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Fri, 08 Nov 2024 19:19:54 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id DC5194002D; Fri, 8 Nov 2024 19:19:11 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 864BA2FAA00; Fri, 8 Nov 2024 19:18:25 +0100 (CET) Received: from jkgcxl0004.jkg.st.com (10.74.22.255) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Fri, 8 Nov 2024 19:18:25 +0100 From: =?utf-8?q?Torbj=C3=B6rn_SVENSSON?= To: CC: , =?utf-8?q?Torbj=C3=B6rn_SVENSSON?= Subject: [PATCH] testsuite: arm: Check that a far jump is used in thumb1-far-jump-2.c Date: Fri, 8 Nov 2024 19:17:54 +0100 Message-ID: <20241108181753.2662923-1-torbjorn.svensson@foss.st.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.74.22.255] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Ok for trunk? --- With the changes in r15-1579-g792f97b44ff, the code used as "padding" in the test case is optimized way. Prevent this optimization by forcing a read of the volatile memory. Also, validate that there is a far jump in the generated assembler. Without this patch, the generated assembler is reduced to: f3: cmp r0, #0 beq .L1 ldr r4, .L6 .L1: bx lr .L7: .align 2 .L6: .word g_0_1 With the patch, the generated assembler is: f3: push {lr} cmp r0, #0 bne .LCB7 bl .L1 @far jump .LCB7: ldr r3, .L6 ldr r3, [r3] ... ldr r3, .L9+976 ldr r4, [r3] b .L10 .L11: .align 2 .L9: .word g_0_3_7_5 ... .word g_0_1 .L10: .L1: pop {pc} gcc/testsuite/ChangeLog: * gcc.target/arm/thumb1-far-jump-2.c: Force a read of volatile memory in macro to avoid optimization. Signed-off-by: Torbjörn SVENSSON --- gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c b/gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c index 78fcafaaf7d..1cf7a0a86e8 100644 --- a/gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c +++ b/gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c @@ -10,7 +10,7 @@ void f3(int i) { #define GO(n) \ extern volatile int g_##n; \ - r4=(int)&g_##n; + r4=(int)g_##n; #define GO8(n) \ GO(n##_0) \ @@ -54,4 +54,5 @@ void f3(int i) } } -/* { dg-final { scan-assembler "push.*lr" } } */ +/* { dg-final { scan-assembler "\tpush.*lr" } } */ +/* { dg-final { scan-assembler "\tbl\t\\.L\[0-9\]+\t@far jump" } } */