diff mbox series

[RFC,3/9] aarch64: add new insn definition for st2g

Message ID 20241107213937.362703-4-indu.bhagat@oracle.com
State New
Headers show
Series Add -fsanitize=memtag | expand

Commit Message

Indu Bhagat Nov. 7, 2024, 9:39 p.m. UTC 
Store Allocation Tags (st2g) is an Armv8.5-A memory tagging (MTE)
instruction. It stores an allocation tag to two tag granules of memory.

TBD:
  - Not too sure what is the best way to generate the st2g yet; A
    subsequent patch will emit them in one of the target hooks.
  - the current define_insn may need fixing.  The construct comparing
    the two offsets should rather be defined as a new predicate?

gcc/ChangeLog:

	* config/aarch64/aarch64.md (st2g): New definition.
---
 gcc/config/aarch64/aarch64.md | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
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Patch

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 1ec872afef71..a2a69a9c0d3e 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -8252,6 +8252,26 @@ 
   [(set_attr "type" "memtag")]
 )
 
+;; ST2G updates allocation tags for two memory granules (i.e. 32 bytes) at
+;; once, without zero initialization.
+(define_insn "st2g"
+  [(set (mem:QI (unspec:DI
+	 [(plus:DI (match_operand:DI 1 "register_operand" "rk")
+		   (match_operand:DI 2 "aarch64_granule16_simm9" "i"))]
+	 UNSPEC_TAG_SPACE))
+	(and:QI (lshiftrt:DI (match_operand:DI 0 "register_operand" "rk")
+			     (const_int 56)) (const_int 15)))
+   (set (mem:QI (unspec:DI
+	 [(plus:DI (match_dup 1)
+		   (match_operand:DI 3 "aarch64_granule16_simm9" "i"))]
+	 UNSPEC_TAG_SPACE))
+	(and:QI (lshiftrt:DI (match_dup 0)
+			     (const_int 56)) (const_int 15)))]
+  "TARGET_MEMTAG && (INTVAL (operands[2]) - 16 == INTVAL (operands[3]))"
+  "st2g\\t%0, [%1, #%2]"
+  [(set_attr "type" "memtag")]
+)
+
 ;; Load/Store 64-bit (LS64) instructions.
 (define_insn "ld64b"
   [(set (match_operand:V8DI 0 "register_operand" "=r")