[v4,8/8] RISC-V: Add else operand to masked loads [PR115336].

Message ID	20241107175753.322338-9-rdapp.gcc@gmail.com
State	New
Headers	show Return-Path: <gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org> DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D33A33858C54 From: Robin Dapp <rdapp.gcc@gmail.com> To: gcc-patches@gcc.gnu.org Cc: rdapp.gcc@gmail.com, rguenther@suse.de, richard.sandiford@arm.com, jeffreyalaw@gmail.com, ams@baylibre.com, crazylht@gmail.com Subject: [PATCH v4 8/8] RISC-V: Add else operand to masked loads [PR115336]. Date: Thu, 7 Nov 2024 18:57:53 +0100 Message-ID: <20241107175753.322338-9-rdapp.gcc@gmail.com> In-Reply-To: <20241107175753.322338-1-rdapp.gcc@gmail.com> References: <20241107175753.322338-1-rdapp.gcc@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org
Series	Add maskload else operand. \| expand [v4,0/8] Add maskload else operand. [v4,1/8] docs: Document maskload else operand and behavior. [v4,2/8] ifn: Add else-operand handling. [v4,3/8] tree-ifcvt: Add zero maskload else value. [v4,4/8] vect: Add maskload else value support. [v4,5/8] aarch64: Add masked-load else operands. [v4,6/8] gcn: Add else operand to masked loads. [v4,7/8] i386: Add zero maskload else operand. [v4,8/8] RISC-V: Add else operand to masked loads [PR115336].

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 1f1849d5237..26489e537c6 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -26,8 +26,9 @@ (define_expand "mask_len_load<mode><vm>" [(match_operand:V 0 "register_operand") (match_operand:V 1 "memory_operand") (match_operand:<VM> 2 "vector_mask_operand") - (match_operand 3 "autovec_length_operand") - (match_operand 4 "const_0_operand")] + (match_operand:V 3 "maskload_else_operand") + (match_operand 4 "autovec_length_operand") + (match_operand 5 "const_0_operand")] "TARGET_VECTOR" { riscv_vector::expand_load_store (operands, true); @@ -57,8 +58,9 @@ (define_expand "mask_len_gather_load<RATIO64:mode><RATIO64I:mode>" (match_operand 3 "<RATIO64:gs_extension>") (match_operand 4 "<RATIO64:gs_scale>") (match_operand:<RATIO64:VM> 5 "vector_mask_operand") - (match_operand 6 "autovec_length_operand") - (match_operand 7 "const_0_operand")] + (match_operand 6 "maskload_else_operand") + (match_operand 7 "autovec_length_operand") + (match_operand 8 "const_0_operand")] "TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_p (<RATIO64I:MODE>mode)" { riscv_vector::expand_gather_scatter (operands, true); @@ -72,8 +74,9 @@ (define_expand "mask_len_gather_load<RATIO32:mode><RATIO32I:mode>" (match_operand 3 "<RATIO32:gs_extension>") (match_operand 4 "<RATIO32:gs_scale>") (match_operand:<RATIO32:VM> 5 "vector_mask_operand") - (match_operand 6 "autovec_length_operand") - (match_operand 7 "const_0_operand")] + (match_operand 6 "maskload_else_operand") + (match_operand 7 "autovec_length_operand") + (match_operand 8 "const_0_operand")] "TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_p (<RATIO32I:MODE>mode)" { riscv_vector::expand_gather_scatter (operands, true); @@ -87,8 +90,9 @@ (define_expand "mask_len_gather_load<RATIO16:mode><RATIO16I:mode>" (match_operand 3 "<RATIO16:gs_extension>") (match_operand 4 "<RATIO16:gs_scale>") (match_operand:<RATIO16:VM> 5 "vector_mask_operand") - (match_operand 6 "autovec_length_operand") - (match_operand 7 "const_0_operand")] + (match_operand 6 "maskload_else_operand") + (match_operand 7 "autovec_length_operand") + (match_operand 8 "const_0_operand")] "TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_p (<RATIO16I:MODE>mode)" { riscv_vector::expand_gather_scatter (operands, true); @@ -102,8 +106,9 @@ (define_expand "mask_len_gather_load<RATIO8:mode><RATIO8I:mode>" (match_operand 3 "<RATIO8:gs_extension>") (match_operand 4 "<RATIO8:gs_scale>") (match_operand:<RATIO8:VM> 5 "vector_mask_operand") - (match_operand 6 "autovec_length_operand") - (match_operand 7 "const_0_operand")] + (match_operand 6 "maskload_else_operand") + (match_operand 7 "autovec_length_operand") + (match_operand 8 "const_0_operand")] "TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_p (<RATIO8I:MODE>mode)" { riscv_vector::expand_gather_scatter (operands, true); @@ -117,8 +122,9 @@ (define_expand "mask_len_gather_load<RATIO4:mode><RATIO4I:mode>" (match_operand 3 "<RATIO4:gs_extension>") (match_operand 4 "<RATIO4:gs_scale>") (match_operand:<RATIO4:VM> 5 "vector_mask_operand") - (match_operand 6 "autovec_length_operand") - (match_operand 7 "const_0_operand")] + (match_operand 6 "maskload_else_operand") + (match_operand 7 "autovec_length_operand") + (match_operand 8 "const_0_operand")] "TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_p (<RATIO4I:MODE>mode)" { riscv_vector::expand_gather_scatter (operands, true); @@ -132,8 +138,9 @@ (define_expand "mask_len_gather_load<RATIO2:mode><RATIO2I:mode>" (match_operand 3 "<RATIO2:gs_extension>") (match_operand 4 "<RATIO2:gs_scale>") (match_operand:<RATIO2:VM> 5 "vector_mask_operand") - (match_operand 6 "autovec_length_operand") - (match_operand 7 "const_0_operand")] + (match_operand 6 "maskload_else_operand") + (match_operand 7 "autovec_length_operand") + (match_operand 8 "const_0_operand")] "TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_p (<RATIO2I:MODE>mode)" { riscv_vector::expand_gather_scatter (operands, true); @@ -151,8 +158,9 @@ (define_expand "mask_len_gather_load<mode><mode>" (match_operand 3 "<gs_extension>") (match_operand 4 "<gs_scale>") (match_operand:<VM> 5 "vector_mask_operand") - (match_operand 6 "autovec_length_operand") - (match_operand 7 "const_0_operand")] + (match_operand 6 "maskload_else_operand") + (match_operand 7 "autovec_length_operand") + (match_operand 8 "const_0_operand")] "TARGET_VECTOR" { riscv_vector::expand_gather_scatter (operands, true); @@ -280,8 +288,9 @@ (define_expand "vec_mask_len_load_lanes<mode><vsingle>" [(match_operand:VT 0 "register_operand") (match_operand:VT 1 "memory_operand") (match_operand:<VM> 2 "vector_mask_operand") - (match_operand 3 "autovec_length_operand") - (match_operand 4 "const_0_operand")] + (match_operand 3 "maskload_else_operand") + (match_operand 4 "autovec_length_operand") + (match_operand 5 "const_0_operand")] "TARGET_VECTOR_AUTOVEC_SEGMENT" { riscv_vector::expand_lanes_load_store (operands, true); @@ -2898,8 +2907,9 @@ (define_expand "mask_len_strided_load_<mode>" (match_operand 1 "pmode_reg_or_0_operand") (match_operand 2 "pmode_reg_or_0_operand") (match_operand:<VM> 3 "vector_mask_operand") - (match_operand 4 "autovec_length_operand") - (match_operand 5 "const_0_operand")] + (match_operand 4 "maskload_else_operand") + (match_operand 5 "autovec_length_operand") + (match_operand 6 "const_0_operand")] "TARGET_VECTOR" { riscv_vector::expand_strided_load (<MODE>mode, operands); diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 55bcfa4fa4f..ffa90948dd7 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -528,6 +528,9 @@ (define_predicate "autovec_else_operand" (ior (match_operand 0 "register_operand") (match_operand 0 "scratch_operand"))) +(define_predicate "maskload_else_operand" + (match_operand 0 "scratch_operand")) + (define_predicate "vector_arith_operand" (ior (match_operand 0 "register_operand") (and (match_code "const_vector") diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 5e728f04cf5..a0e22b6454b 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -3793,12 +3793,23 @@ expand_select_vl (rtx *ops) emit_insn (gen_no_side_effects_vsetvl_rtx (rvv_mode, ops[0], ops[1])); } +/* Return RVV_VUNDEF if the ELSE value is scratch rtx. */ +static rtx +get_else_operand (rtx op) +{ + return GET_CODE (op) == SCRATCH ? RVV_VUNDEF (GET_MODE (op)) : op; +} + /* Expand MASK_LEN_{LOAD,STORE}. */ void expand_load_store (rtx *ops, bool is_load) { - rtx mask = ops[2]; - rtx len = ops[3]; + int idx = 2; + rtx mask = ops[idx++]; + /* A masked load has a merge/else operand. */ + if (is_load) + get_else_operand (ops[idx++]); + rtx len = ops[idx]; machine_mode mode = GET_MODE (ops[0]); if (is_vlmax_len_p (mode, len)) @@ -3841,7 +3852,9 @@ expand_strided_load (machine_mode mode, rtx *ops) rtx base = ops[1]; rtx stride = ops[2]; rtx mask = ops[3]; - rtx len = ops[4]; + int idx = 4; + get_else_operand (ops[idx++]); + rtx len = ops[idx]; poly_int64 len_val; insn_code icode = code_for_pred_strided_load (mode); @@ -3943,13 +3956,6 @@ expand_cond_len_op (unsigned icode, insn_flags op_type, rtx *ops, rtx len) emit_nonvlmax_insn (icode, insn_flags, ops, len); } -/* Return RVV_VUNDEF if the ELSE value is scratch rtx. */ -static rtx -get_else_operand (rtx op) -{ - return GET_CODE (op) == SCRATCH ? RVV_VUNDEF (GET_MODE (op)) : op; -} - /* Expand unary ops COND_LEN_*. */ void expand_cond_len_unop (unsigned icode, rtx *ops) @@ -4070,6 +4076,8 @@ expand_gather_scatter (rtx *ops, bool is_load) int shift; rtx mask = ops[5]; rtx len = ops[6]; + if (is_load) + len = ops[7]; if (is_load) { vec_reg = ops[0]; @@ -4292,6 +4300,8 @@ expand_lanes_load_store (rtx *ops, bool is_load) { rtx mask = ops[2]; rtx len = ops[3]; + if (is_load) + len = ops[4]; rtx addr = is_load ? XEXP (ops[1], 0) : XEXP (ops[0], 0); rtx reg = is_load ? ops[0] : ops[1]; machine_mode mode = GET_MODE (ops[0]); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr115336.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr115336.c new file mode 100644 index 00000000000..aa2d02309be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr115336.c @@ -0,0 +1,20 @@ +/* { dg-do run } */ +/* { dg-options { -O3 -march=rv64gcv_zvl256b -mabi=lp64d } } */ +/* { dg-require-effective-target rvv_zvl256b_ok } */ + +short d[19]; +_Bool e[100][19][19]; +_Bool f[10000]; + +int main() +{ + for (long g = 0; g < 19; ++g) + d[g] = 3; + _Bool(*h)[19][19] = e; + for (short g = 0; g < 9; g++) + for (int i = 4; i < 16; i += 3) + f[i * 9 + g] = d[i] ? d[i] : h[g][i][2]; + for (long i = 120; i < 122; ++i) + if (f[i] != 1) + __builtin_abort (); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr116059.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr116059.c new file mode 100644 index 00000000000..93700acd485 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr116059.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-add-options riscv_v } */ +/* { dg-additional-options "-O2 -std=gnu99" } */ + +char a; +_Bool b[11] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}; +int main() { + _Bool *c = b; + for (signed d = 0; d < 11; d += 1) + a = d % 2 == 0 ? c[d] / c[d] + : c[d]; + if (a != 1) + __builtin_abort (); +}

[v4,8/8] RISC-V: Add else operand to masked loads [PR115336].

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