Message ID | 20241106114613.2972987-2-tejas.belagod@arm.com |
---|---|
State | New |
Headers | show
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Wed, 6 Nov 2024 11:46:19 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 6 Nov 2024 11:46:19 +0000 Received: from a078660.blr.arm.com (10.162.46.14) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Wed, 6 Nov 2024 11:46:17 +0000 From: Tejas Belagod <tejas.belagod@arm.com> To: <gcc-patches@gcc.gnu.org> CC: Tejas Belagod <tejas.belagod@arm.com>, <richard.sandiford@arm.com>, <josmyers@redhat.com>, <jason@redhat.com>, <polacek@redhat.com> Subject: [PATCH 01/10] aarch64: Fix ACLE macro __ARM_FEATURE_SVE_VECTOR_OPERATORS Date: Wed, 6 Nov 2024 17:16:04 +0530 Message-ID: <20241106114613.2972987-2-tejas.belagod@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241106114613.2972987-1-tejas.belagod@arm.com> References: <20241106114613.2972987-1-tejas.belagod@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DU6PEPF00009524:EE_|VI1PR08MB5501:EE_|AM3PEPF0000A790:EE_|DU4PR08MB10984:EE_ X-MS-Office365-Filtering-Correlation-Id: 89e93e9f-2e11-4504-0b03-08dcfe58ab36 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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Series |
aarch64: Enable C/C++ operations on SVE ACLE types.
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expand
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diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc index f9b9e379375..c71a3af8406 100644 --- a/gcc/config/aarch64/aarch64-c.cc +++ b/gcc/config/aarch64/aarch64-c.cc @@ -193,15 +193,19 @@ aarch64_update_cpp_builtins (cpp_reader *pfile) aarch64_def_or_undef (TARGET_SIMD_RDMA, "__ARM_FEATURE_QRDMX", pfile); aarch64_def_or_undef (TARGET_SVE, "__ARM_FEATURE_SVE", pfile); cpp_undef (pfile, "__ARM_FEATURE_SVE_BITS"); + cpp_undef (pfile, "__ARM_FEATURE_SVE_VECTOR_OPERATORS"); if (TARGET_SVE) { int bits; + int ops = 1; if (!BITS_PER_SVE_VECTOR.is_constant (&bits)) - bits = 0; + { + bits = 0; + ops = 2; + } builtin_define_with_int_value ("__ARM_FEATURE_SVE_BITS", bits); + builtin_define_with_int_value ("__ARM_FEATURE_SVE_VECTOR_OPERATORS", ops); } - aarch64_def_or_undef (TARGET_SVE, "__ARM_FEATURE_SVE_VECTOR_OPERATORS", - pfile); aarch64_def_or_undef (TARGET_SVE_I8MM, "__ARM_FEATURE_SVE_MATMUL_INT8", pfile); aarch64_def_or_undef (TARGET_SVE_F32MM,