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X-CSE-ConnectionGUID: Ytq+Lkf6RZ6oBjKeYas+Lg== X-CSE-MsgGUID: 7lZVkmS4SPWLNwW1B3YBYw== X-IronPort-AV: E=McAfee;i="6700,10204,11225"; a="27792718" X-IronPort-AV: E=Sophos;i="6.11,204,1725346800"; d="scan'208";a="27792718" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2024 23:09:36 -0700 X-CSE-ConnectionGUID: sLMCToYfRJaXXUfbckEx3A== X-CSE-MsgGUID: 6t6KMD5lQge6ee9AbGyvrw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,204,1725346800"; d="scan'208";a="77652836" Received: from scymds04.sc.intel.com ([10.82.73.238]) by orviesa009.jf.intel.com with ESMTP; 14 Oct 2024 23:09:36 -0700 Received: from shgcc10.sh.intel.com (shgcc10.sh.intel.com [10.239.85.189]) by scymds04.sc.intel.com (Postfix) with ESMTP id 22CC32003ACC; Mon, 14 Oct 2024 23:09:34 -0700 (PDT) From: "Cui, Lili" To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH] Support andn_optab for x86 Date: Tue, 15 Oct 2024 14:09:34 +0800 Message-Id: <20241015060934.1181090-1-lili.cui@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Hi all, This patch is to add andn_optab for x86. Bootstrapped and regtested on x86-64-linux-pc, OK for trunk? Regards, Lili. Add new andn pattern to match the new optab added by r15-1890-gf379596e0ba99d. Only enable 64bit, 128bit and 256bit vector ANDN, X86-64 has mask mov instruction when avx512 is enabled. gcc/ChangeLog: * config/i386/sse.md (andn3): New. * config/i386/mmx.md (andn3): New. gcc/testsuite/ChangeLog: * g++.target/i386/vect-cmp.C: New test. --- gcc/config/i386/mmx.md | 7 +++++++ gcc/config/i386/sse.md | 7 +++++++ gcc/testsuite/g++.target/i386/vect-cmp.C | 23 +++++++++++++++++++++++ 3 files changed, 37 insertions(+) create mode 100644 gcc/testsuite/g++.target/i386/vect-cmp.C diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 9d2a82c598e..ef4ed8b501a 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -4467,6 +4467,13 @@ operands[0] = lowpart_subreg (V16QImode, operands[0], mode); }) +(define_expand "andn3" + [(set (match_operand:MMXMODEI 0 "register_operand") + (and:MMXMODEI + (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand")) + (match_operand:MMXMODEI 2 "register_operand")))] + "TARGET_SSE2") + (define_insn "mmx_andnot3" [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x,v") (and:MMXMODEI diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index a45b50ad732..7be31334667 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -18438,6 +18438,13 @@ (match_operand:VI_AVX2 2 "vector_operand")))] "TARGET_SSE2") +(define_expand "andn3" + [(set (match_operand:VI 0 "register_operand") + (and:VI + (not:VI (match_operand:VI 2 "register_operand")) + (match_operand:VI 1 "register_operand")))] + "TARGET_SSE2") + (define_expand "_andnot3_mask" [(set (match_operand:VI48_AVX512VL 0 "register_operand") (vec_merge:VI48_AVX512VL diff --git a/gcc/testsuite/g++.target/i386/vect-cmp.C b/gcc/testsuite/g++.target/i386/vect-cmp.C new file mode 100644 index 00000000000..c154474fa51 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/vect-cmp.C @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v3 -fdump-tree-optimized" } */ + +#define vect8 __attribute__((vector_size(8) )) +#define vect16 __attribute__((vector_size(16) )) +#define vect32 __attribute__((vector_size(32) )) + +vect8 int bar0 (vect8 float a, vect8 float b, vect8 int c) +{ + return (a > b) ? 0 : c; +} + +vect16 int bar1 (vect16 float a, vect16 float b, vect16 int c) +{ + return (a > b) ? 0 : c; +} + +vect32 int bar2 (vect32 float a, vect32 float b, vect32 int c) +{ + return (a > b) ? 0 : c; +} + +/* { dg-final { scan-tree-dump-times ".BIT_ANDN " 3 "optimized" { target { ! ia32 } } } } */