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X-CSE-ConnectionGUID: nYPwVQiPQ4a40q3mTiDQRg== X-CSE-MsgGUID: u9xjoc7hSZKEzUOXZRx3WQ== X-IronPort-AV: E=McAfee;i="6700,10204,11225"; a="28465098" X-IronPort-AV: E=Sophos;i="6.11,204,1725346800"; d="scan'208";a="28465098" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2024 20:29:59 -0700 X-CSE-ConnectionGUID: MNVfrlAxQQSxbshToO4YGw== X-CSE-MsgGUID: Zv6dmxV2TSafSWHjizWMHQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,204,1725346800"; d="scan'208";a="82381280" Received: from shliclel4217.sh.intel.com ([10.239.240.127]) by fmviesa004.fm.intel.com with ESMTP; 14 Oct 2024 20:29:58 -0700 From: liuhongt To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, jeffreyalaw@gmail.com Subject: [PATCH 2/2] [x86] Canonicalize (vec_merge (fma: op2 op1 op3) (match_dup 1)) mask) to (vec_merge (fma: op1 op2 op3) (match_dup 1)) mask) Date: Tue, 15 Oct 2024 11:29:55 +0800 Message-Id: <20241015032955.3677006-3-hongtao.liu@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20241015032955.3677006-1-hongtao.liu@intel.com> References: <7p8r18n6-668q-37pr-7o70-74rr02673919@fhfr.qr> <20241015032955.3677006-1-hongtao.liu@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org For masked FMA, there're 2 forms of RTL representation 1) (vec_merge (fma: op2 op1 op3) op1) mask) 2) (vec_merge (fma: op1 op2 op3) op1) mask) It's because op1 op2 are communatative in RTL(the second op1 is written as (match_dup 1)) we once tried to replace (match_dup 1) with (match_operand:VFH_AVX512VL 5 "nonimmediate_operand" "0,0")), but trigger an ICE in reload(reload can handle at most one operand with "0" constraint). So the patch do the canonicalizaton for the backend part. gcc/ChangeLog: PR target/117072 (_fmadd__mask): Relax predicates of fma operands from register_operand to nonimmediate_operand (_fmadd__mask3): Ditto. (_fmsub__mask): Ditto. (_fmsub__mask3): Ditto. (_fnmadd__mask): Ditto. (_fnmadd__mask3): Ditto. (_fnmsub__mask): Ditto. (_fnmsub__mask3): Ditto. (_fmaddsub__mask3): Ditto. (_fmsubadd__mask): Ditto. (_fmsubadd__mask3): Ditto. (avx512f_vmfmadd__mask): Ditto. (avx512f_vmfmadd__mask3): Ditto. (avx512f_vmfmadd__maskz_1): Ditto. (*avx512f_vmfmsub__mask): Ditto. (avx512f_vmfmsub__mask3): Ditto. (*avx512f_vmfmsub__maskz_1): Ditto. (avx512f_vmfnmadd__mask): Ditto. (avx512f_vmfnmadd__mask3): Ditto. (avx512f_vmfnmadd__maskz_1): Ditto. (*avx512f_vmfnmsub__mask): Ditto. (*avx512f_vmfnmsub__mask3): Ditto. (*avx512f_vmfnmsub__maskz_1): Ditto. (avx10_2_fmaddnepbf16__mask3): Ditto. (avx10_2_fnmaddnepbf16__mask3): Ditto. (avx10_2_fmsubnepbf16__mask3): Ditto. (avx10_2_fnmsubnepbf16__mask3): Ditto. (fmai_vmfmadd_): Swap operands[1] and operands[2]. (fmai_vmfmsub_): Ditto. (fmai_vmfnmadd_): Ditto. (fmai_vmfnmsub_): Ditto. (*fmai_fmadd_): Swap operands[1] and operands[2] adjust operands[1] predicates from register_operand to nonimmediate_operand. (*fmai_fmsub_): Ditto. (*fmai_fnmadd_): Ditto. (*fmai_fnmsub_): Ditto. --- gcc/config/i386/sse.md | 86 +++++++++++++++++++++--------------------- 1 file changed, 43 insertions(+), 43 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index a45b50ad732..9201b1a0782 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -5895,7 +5895,7 @@ (define_insn "_fmadd__mask" [(set (match_operand:VFH_AVX512VL 0 "register_operand" "=v,v") (vec_merge:VFH_AVX512VL (fma:VFH_AVX512VL - (match_operand:VFH_AVX512VL 1 "register_operand" "0,0") + (match_operand:VFH_AVX512VL 1 "nonimmediate_operand" "0,0") (match_operand:VFH_AVX512VL 2 "" ",v") (match_operand:VFH_AVX512VL 3 "" "v,")) (match_dup 1) @@ -5914,7 +5914,7 @@ (define_insn "_fmadd__mask3" (fma:VFH_AVX512VL (match_operand:VFH_AVX512VL 1 "" "%v") (match_operand:VFH_AVX512VL 2 "" "") - (match_operand:VFH_AVX512VL 3 "register_operand" "0")) + (match_operand:VFH_AVX512VL 3 "nonimmediate_operand" "0")) (match_dup 3) (match_operand: 4 "register_operand" "Yk")))] "TARGET_AVX512F && " @@ -5999,7 +5999,7 @@ (define_insn "_fmsub__mask" [(set (match_operand:VFH_AVX512VL 0 "register_operand" "=v,v") (vec_merge:VFH_AVX512VL (fma:VFH_AVX512VL - (match_operand:VFH_AVX512VL 1 "register_operand" "0,0") + (match_operand:VFH_AVX512VL 1 "nonimmediate_operand" "0,0") (match_operand:VFH_AVX512VL 2 "" ",v") (neg:VFH_AVX512VL (match_operand:VFH_AVX512VL 3 "" "v,"))) @@ -6020,7 +6020,7 @@ (define_insn "_fmsub__mask3" (match_operand:VFH_AVX512VL 1 "" "%v") (match_operand:VFH_AVX512VL 2 "" "") (neg:VFH_AVX512VL - (match_operand:VFH_AVX512VL 3 "register_operand" "0"))) + (match_operand:VFH_AVX512VL 3 "nonimmediate_operand" "0"))) (match_dup 3) (match_operand: 4 "register_operand" "Yk")))] "TARGET_AVX512F && " @@ -6106,7 +6106,7 @@ (define_insn "_fnmadd__mask" (vec_merge:VFH_AVX512VL (fma:VFH_AVX512VL (neg:VFH_AVX512VL - (match_operand:VFH_AVX512VL 1 "register_operand" "0,0")) + (match_operand:VFH_AVX512VL 1 "nonimmediate_operand" "0,0")) (match_operand:VFH_AVX512VL 2 "" ",v") (match_operand:VFH_AVX512VL 3 "" "v,")) (match_dup 1) @@ -6126,7 +6126,7 @@ (define_insn "_fnmadd__mask3" (neg:VFH_AVX512VL (match_operand:VFH_AVX512VL 1 "" "%v")) (match_operand:VFH_AVX512VL 2 "" "") - (match_operand:VFH_AVX512VL 3 "register_operand" "0")) + (match_operand:VFH_AVX512VL 3 "nonimmediate_operand" "0")) (match_dup 3) (match_operand: 4 "register_operand" "Yk")))] "TARGET_AVX512F && " @@ -6215,7 +6215,7 @@ (define_insn "_fnmsub__mask" (vec_merge:VFH_AVX512VL (fma:VFH_AVX512VL (neg:VFH_AVX512VL - (match_operand:VFH_AVX512VL 1 "register_operand" "0,0")) + (match_operand:VFH_AVX512VL 1 "nonimmediate_operand" "0,0")) (match_operand:VFH_AVX512VL 2 "" ",v") (neg:VFH_AVX512VL (match_operand:VFH_AVX512VL 3 "" "v,"))) @@ -6237,7 +6237,7 @@ (define_insn "_fnmsub__mask3" (match_operand:VFH_AVX512VL 1 "" "%v")) (match_operand:VFH_AVX512VL 2 "" "") (neg:VFH_AVX512VL - (match_operand:VFH_AVX512VL 3 "register_operand" "0"))) + (match_operand:VFH_AVX512VL 3 "nonimmediate_operand" "0"))) (match_dup 3) (match_operand: 4 "register_operand" "Yk")))] "TARGET_AVX512F && " @@ -6369,9 +6369,9 @@ (define_insn "_fmaddsub__mask3" [(set (match_operand:VFH_AVX512VL 0 "register_operand" "=v") (vec_merge:VFH_AVX512VL (unspec:VFH_AVX512VL - [(match_operand:VFH_AVX512VL 1 "register_operand" "v") + [(match_operand:VFH_AVX512VL 1 "nonimmediate_operand" "v") (match_operand:VFH_AVX512VL 2 "" "") - (match_operand:VFH_AVX512VL 3 "register_operand" "0")] + (match_operand:VFH_AVX512VL 3 "nonimmediate_operand" "0")] UNSPEC_FMADDSUB) (match_dup 3) (match_operand: 4 "register_operand" "Yk")))] @@ -6421,7 +6421,7 @@ (define_insn "_fmsubadd__mask" [(set (match_operand:VFH_AVX512VL 0 "register_operand" "=v,v") (vec_merge:VFH_AVX512VL (unspec:VFH_AVX512VL - [(match_operand:VFH_AVX512VL 1 "register_operand" "0,0") + [(match_operand:VFH_AVX512VL 1 "nonimmediate_operand" "0,0") (match_operand:VFH_AVX512VL 2 "" ",v") (neg:VFH_AVX512VL (match_operand:VFH_AVX512VL 3 "" "v,"))] @@ -6440,10 +6440,10 @@ (define_insn "_fmsubadd__mask3" [(set (match_operand:VFH_AVX512VL 0 "register_operand" "=v") (vec_merge:VFH_AVX512VL (unspec:VFH_AVX512VL - [(match_operand:VFH_AVX512VL 1 "register_operand" "v") + [(match_operand:VFH_AVX512VL 1 "nonimmediate_operand" "v") (match_operand:VFH_AVX512VL 2 "" "") (neg:VFH_AVX512VL - (match_operand:VFH_AVX512VL 3 "register_operand" "0"))] + (match_operand:VFH_AVX512VL 3 "nonimmediate_operand" "0"))] UNSPEC_FMADDSUB) (match_dup 3) (match_operand: 4 "register_operand" "Yk")))] @@ -6460,7 +6460,7 @@ (define_expand "fmai_vmfmadd_" [(set (match_operand:VFH_128 0 "register_operand") (vec_merge:VFH_128 (fma:VFH_128 - (match_operand:VFH_128 1 "register_operand") + (match_operand:VFH_128 1 "nonimmediate_operand") (match_operand:VFH_128 2 "") (match_operand:VFH_128 3 "")) (match_dup 1) @@ -6471,7 +6471,7 @@ (define_expand "fmai_vmfmsub_" [(set (match_operand:VFH_128 0 "register_operand") (vec_merge:VFH_128 (fma:VFH_128 - (match_operand:VFH_128 1 "register_operand") + (match_operand:VFH_128 1 "nonimmediate_operand") (match_operand:VFH_128 2 "") (neg:VFH_128 (match_operand:VFH_128 3 ""))) @@ -6484,8 +6484,8 @@ (define_expand "fmai_vmfnmadd_" (vec_merge:VFH_128 (fma:VFH_128 (neg:VFH_128 - (match_operand:VFH_128 2 "")) - (match_operand:VFH_128 1 "register_operand") + (match_operand:VFH_128 1 "nonimmediate_operand")) + (match_operand:VFH_128 2 "") (match_operand:VFH_128 3 "")) (match_dup 1) (const_int 1)))] @@ -6496,8 +6496,8 @@ (define_expand "fmai_vmfnmsub_" (vec_merge:VFH_128 (fma:VFH_128 (neg:VFH_128 - (match_operand:VFH_128 2 "")) - (match_operand:VFH_128 1 "register_operand") + (match_operand:VFH_128 1 "nonimmediate_operand")) + (match_operand:VFH_128 2 "") (neg:VFH_128 (match_operand:VFH_128 3 ""))) (match_dup 1) @@ -6508,7 +6508,7 @@ (define_insn "*fmai_fmadd_" [(set (match_operand:VFH_128 0 "register_operand" "=v,v") (vec_merge:VFH_128 (fma:VFH_128 - (match_operand:VFH_128 1 "register_operand" "0,0") + (match_operand:VFH_128 1 "nonimmediate_operand" "0,0") (match_operand:VFH_128 2 "" ", v") (match_operand:VFH_128 3 "" "v,")) (match_dup 1) @@ -6525,7 +6525,7 @@ (define_insn "*fmai_fmsub_" [(set (match_operand:VFH_128 0 "register_operand" "=v,v") (vec_merge:VFH_128 (fma:VFH_128 - (match_operand:VFH_128 1 "register_operand" "0,0") + (match_operand:VFH_128 1 "nonimmediate_operand" "0,0") (match_operand:VFH_128 2 "" ",v") (neg:VFH_128 (match_operand:VFH_128 3 "" "v,"))) @@ -6544,8 +6544,8 @@ (define_insn "*fmai_fnmadd_" (vec_merge:VFH_128 (fma:VFH_128 (neg:VFH_128 - (match_operand:VFH_128 2 "" ",v")) - (match_operand:VFH_128 1 "register_operand" "0,0") + (match_operand:VFH_128 1 "nonimmediate_operand" "0,0")) + (match_operand:VFH_128 2 "" ",v") (match_operand:VFH_128 3 "" "v,")) (match_dup 1) (const_int 1)))] @@ -6562,8 +6562,8 @@ (define_insn "*fmai_fnmsub_" (vec_merge:VFH_128 (fma:VFH_128 (neg:VFH_128 - (match_operand:VFH_128 2 "" ",v")) - (match_operand:VFH_128 1 "register_operand" "0,0") + (match_operand:VFH_128 1 "nonimmediate_operand" "0,0")) + (match_operand:VFH_128 2 "" ",v") (neg:VFH_128 (match_operand:VFH_128 3 "" "v,"))) (match_dup 1) @@ -6581,7 +6581,7 @@ (define_insn "avx512f_vmfmadd__mask" (vec_merge:VFH_128 (vec_merge:VFH_128 (fma:VFH_128 - (match_operand:VFH_128 1 "register_operand" "0,0") + (match_operand:VFH_128 1 "nonimmediate_operand" "0,0") (match_operand:VFH_128 2 "" ",v") (match_operand:VFH_128 3 "" "v,")) (match_dup 1) @@ -6603,7 +6603,7 @@ (define_insn "avx512f_vmfmadd__mask3" (fma:VFH_128 (match_operand:VFH_128 1 "" "%v") (match_operand:VFH_128 2 "" "") - (match_operand:VFH_128 3 "register_operand" "0")) + (match_operand:VFH_128 3 "nonimmediate_operand" "0")) (match_dup 3) (match_operand:QI 4 "register_operand" "Yk")) (match_dup 3) @@ -6633,7 +6633,7 @@ (define_insn "avx512f_vmfmadd__maskz_1" (vec_merge:VFH_128 (vec_merge:VFH_128 (fma:VFH_128 - (match_operand:VFH_128 1 "register_operand" "0,0") + (match_operand:VFH_128 1 "nonimmediate_operand" "0,0") (match_operand:VFH_128 2 "" ",v") (match_operand:VFH_128 3 "" "v,")) (match_operand:VFH_128 4 "const0_operand") @@ -6653,7 +6653,7 @@ (define_insn "*avx512f_vmfmsub__mask" (vec_merge:VFH_128 (vec_merge:VFH_128 (fma:VFH_128 - (match_operand:VFH_128 1 "register_operand" "0,0") + (match_operand:VFH_128 1 "nonimmediate_operand" "0,0") (match_operand:VFH_128 2 "" ",v") (neg:VFH_128 (match_operand:VFH_128 3 "" "v,"))) @@ -6677,7 +6677,7 @@ (define_insn "avx512f_vmfmsub__mask3" (match_operand:VFH_128 1 "" "%v") (match_operand:VFH_128 2 "" "") (neg:VFH_128 - (match_operand:VFH_128 3 "register_operand" "0"))) + (match_operand:VFH_128 3 "nonimmediate_operand" "0"))) (match_dup 3) (match_operand:QI 4 "register_operand" "Yk")) (match_dup 3) @@ -6693,7 +6693,7 @@ (define_insn "*avx512f_vmfmsub__maskz_1" (vec_merge:VFH_128 (vec_merge:VFH_128 (fma:VFH_128 - (match_operand:VFH_128 1 "register_operand" "0,0") + (match_operand:VFH_128 1 "nonimmediate_operand" "0,0") (match_operand:VFH_128 2 "" ",v") (neg:VFH_128 (match_operand:VFH_128 3 "" "v,"))) @@ -6715,8 +6715,8 @@ (define_insn "avx512f_vmfnmadd__mask" (vec_merge:VFH_128 (fma:VFH_128 (neg:VFH_128 - (match_operand:VFH_128 2 "" ",v")) - (match_operand:VFH_128 1 "register_operand" "0,0") + (match_operand:VFH_128 1 "nonimmediate_operand" "0,0")) + (match_operand:VFH_128 2 "" ",v") (match_operand:VFH_128 3 "" "v,")) (match_dup 1) (match_operand:QI 4 "register_operand" "Yk,Yk")) @@ -6738,7 +6738,7 @@ (define_insn "avx512f_vmfnmadd__mask3" (neg:VFH_128 (match_operand:VFH_128 2 "" "")) (match_operand:VFH_128 1 "" "%v") - (match_operand:VFH_128 3 "register_operand" "0")) + (match_operand:VFH_128 3 "nonimmediate_operand" "0")) (match_dup 3) (match_operand:QI 4 "register_operand" "Yk")) (match_dup 3) @@ -6770,7 +6770,7 @@ (define_insn "avx512f_vmfnmadd__maskz_1" (fma:VFH_128 (neg:VFH_128 (match_operand:VFH_128 2 "" ",v")) - (match_operand:VFH_128 1 "register_operand" "0,0") + (match_operand:VFH_128 1 "nonimmediate_operand" "0,0") (match_operand:VFH_128 3 "" "v,")) (match_operand:VFH_128 4 "const0_operand") (match_operand:QI 5 "register_operand" "Yk,Yk")) @@ -6790,8 +6790,8 @@ (define_insn "*avx512f_vmfnmsub__mask" (vec_merge:VFH_128 (fma:VFH_128 (neg:VFH_128 - (match_operand:VFH_128 2 "" ",v")) - (match_operand:VFH_128 1 "register_operand" "0,0") + (match_operand:VFH_128 1 "nonimmediate_operand" "0,0")) + (match_operand:VFH_128 2 "" ",v") (neg:VFH_128 (match_operand:VFH_128 3 "" "v,"))) (match_dup 1) @@ -6815,7 +6815,7 @@ (define_insn "*avx512f_vmfnmsub__mask3" (match_operand:VFH_128 2 "" "")) (match_operand:VFH_128 1 "" "%v") (neg:VFH_128 - (match_operand:VFH_128 3 "register_operand" "0"))) + (match_operand:VFH_128 3 "nonimmediate_operand" "0"))) (match_dup 3) (match_operand:QI 4 "register_operand" "Yk")) (match_dup 3) @@ -6833,7 +6833,7 @@ (define_insn "*avx512f_vmfnmsub__maskz_1" (fma:VFH_128 (neg:VFH_128 (match_operand:VFH_128 2 "" ",v")) - (match_operand:VFH_128 1 "register_operand" "0,0") + (match_operand:VFH_128 1 "nonimmediate_operand" "0,0") (neg:VFH_128 (match_operand:VFH_128 3 "" "v,"))) (match_operand:VFH_128 4 "const0_operand") @@ -32048,7 +32048,7 @@ (define_insn "avx10_2_fmaddnepbf16__mask3" (fma:VBF_AVX10_2 (match_operand:VBF_AVX10_2 1 "nonimmediate_operand" "%v") (match_operand:VBF_AVX10_2 2 "nonimmediate_operand" "vm") - (match_operand:VBF_AVX10_2 3 "register_operand" "0")) + (match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "0")) (match_dup 3) (match_operand: 4 "register_operand" "Yk")))] "TARGET_AVX10_2_256" @@ -32113,7 +32113,7 @@ (define_insn "avx10_2_fnmaddnepbf16__mask3" (neg:VBF_AVX10_2 (match_operand:VBF_AVX10_2 1 "nonimmediate_operand" "%v")) (match_operand:VBF_AVX10_2 2 "nonimmediate_operand" "vm") - (match_operand:VBF_AVX10_2 3 "register_operand" "0")) + (match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "0")) (match_dup 3) (match_operand: 4 "register_operand" "Yk")))] "TARGET_AVX10_2_256" @@ -32178,7 +32178,7 @@ (define_insn "avx10_2_fmsubnepbf16__mask3" (match_operand:VBF_AVX10_2 1 "nonimmediate_operand" "%v") (match_operand:VBF_AVX10_2 2 "nonimmediate_operand" "vm") (neg:VBF_AVX10_2 - (match_operand:VBF_AVX10_2 3 "register_operand" "0"))) + (match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "0"))) (match_dup 3) (match_operand: 4 "register_operand" "Yk")))] "TARGET_AVX10_2_256" @@ -32246,7 +32246,7 @@ (define_insn "avx10_2_fnmsubnepbf16__mask3" (match_operand:VBF_AVX10_2 1 "nonimmediate_operand" "%v")) (match_operand:VBF_AVX10_2 2 "nonimmediate_operand" "vm") (neg:VBF_AVX10_2 - (match_operand:VBF_AVX10_2 3 "register_operand" "0"))) + (match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "0"))) (match_dup 3) (match_operand: 4 "register_operand" "Yk")))] "TARGET_AVX10_2_256"