From patchwork Tue Oct 15 01:41:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1997159 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=feZ4n3z9; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XSH1T071zz1xv6 for ; Tue, 15 Oct 2024 12:43:20 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 70C4C385AC32 for ; Tue, 15 Oct 2024 01:43:18 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by sourceware.org (Postfix) with ESMTPS id 542E93857000 for ; Tue, 15 Oct 2024 01:42:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 542E93857000 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 542E93857000 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1728956577; cv=none; b=TZBXQau3C4U5+knhyP0kEj33YGlZSlLVGpEeIV2QJSvNLIsf6zExA9PY/RxoRlfgOxWJjFDJrmABKjvaR11ZgcvgkoGynq1BS656dZGs0GKnA1h3gBoWbJxBd3nzYumMoTcS7cCrz9qIynVw/iFxpCbQLSRgnm5Nk1VVtm/sRCQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1728956577; c=relaxed/simple; bh=YnfSScfvIkzK/MvgD44jqr75EZukkXny76U7WTBurxQ=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=Z3wFaZ7BWHWeCxWY8UCY5mY+edGmgiTyqUta7+1Kwnju5f8j6O8LX+8XMtp9HwQRpvYBynogAhGQaJyxArOgjFCwEusKhXwD4KKrSxX5PcqX8ZHb78bCGnA/88uv4IX/smz5hX01xEw6rpwmYsYCZpn72CYsVLP4Ot3j64Q1Yp8= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728956576; x=1760492576; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=YnfSScfvIkzK/MvgD44jqr75EZukkXny76U7WTBurxQ=; b=feZ4n3z9W3hYvOcMLPXIvDf1cumOfjbot5ozZ1IkhlnmS7q5Ugzko5/B +mwMrsADVzuIE7o7RVCLKf4kVfNRf7HWMRjQNtm6o0i1uCzCAbc8cLwpu 6vowLesECo0YbrivGa90653tuIBoxmygZ4DNpNvtAqvX8V8ixvi7feMP8 8+FUxQsWR6mLoY2k0gRqUzbeFaBziQWl3Mza/IyEaZnB3dtKkZtspCvSF 4cMSn9uvE5m0SnFyM7Ig7H+HbathbJDV4o/nzu4KotCUCH5RLsMd4MyOS V/Nrs5zhxjcb0MUlfyO2qrKIuKS0QuVvJNp7hU1+PDdje13Fsi7v/9wsE Q==; X-CSE-ConnectionGUID: EaBzBwqlSbeptsTMoDnzOA== X-CSE-MsgGUID: 52MyxRP/Rj+bQyy6IZBEHQ== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="28474589" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="28474589" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2024 18:42:54 -0700 X-CSE-ConnectionGUID: JbR0x3OVQhS2RqDSGmLMiA== X-CSE-MsgGUID: EbLwsQgQQ8CWyn+uamG6IQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,204,1725346800"; d="scan'208";a="77913646" Received: from panli.sh.intel.com ([10.239.154.73]) by orviesa006.jf.intel.com with ESMTP; 14 Oct 2024 18:42:52 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH] RISC-V: Fix UNRESOLVED testcases for SAT alu vector mode Date: Tue, 15 Oct 2024 09:41:18 +0800 Message-ID: <20241015014118.1701787-1-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li Some saturation related alu testcases missed additional option for expand check, which result in some UNRESOLVED issues. This patch would like to fix it by adding the option back as other testcases. The below test are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: Add compile option for expanding check. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c: Ditto. Signed-off-by: Pan Li --- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c | 1 + .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c | 1 + .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c | 1 + .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c | 1 + .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c | 1 + .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c | 1 + .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c | 1 + .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c | 1 + 8 files changed, 8 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c index 236fe68123f..1320b05e76c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c index 2eda4197abb..e71758d9c4e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c index ae97fece59b..1626e857d28 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c index f0c5289764f..8792bb6112b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c index 7cde4c9d378..4a93c7f89cb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c index 341226838a3..bc6d441759f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c index 17e176b87db..d2239d3e42c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c index 1ebf5c88d3a..9c671cb897b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h"