From patchwork Wed Oct 2 17:13:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 1992117 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XJhJt6mYfz1xt3 for ; Thu, 3 Oct 2024 03:15:26 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CB57A385DDCE for ; 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bh=+lac/pzqVvtuwJNj1IPe3pjmzaLQUjWvT+9CnZ5EORk=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=PaBTuTGInk8soT8Wzy0lZQTmpX+pCdX0loOsiKO1Z8JWG7SEYT+/tD+/+/WE/CY19bamgSFm++Ft1s0yOO8BHt8xNPgf3sIhtN8cPIa/H07XA7b+jHWXl8sEH7R3jCsNHUj3qFwGdKuxPG2fSOw7uLUsF+maxMl7901R/qY+9GA= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 840C8339; Wed, 2 Oct 2024 10:14:32 -0700 (PDT) Received: from e107157-lin.cambridge.arm.com (e107157-lin.cambridge.arm.com [10.2.78.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 60D553F64C; Wed, 2 Oct 2024 10:14:02 -0700 (PDT) From: Andre Vieira To: gcc-patches@gcc.gnu.org Cc: richard.sandiford@arm.com, Andre Vieira Subject: [PATCH 1/2] aarch64: Split FCMA feature bit from Armv8.3-A Date: Wed, 2 Oct 2024 18:13:38 +0100 Message-Id: <20241002171339.299940-2-andre.simoesdiasvieira@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241002171339.299940-1-andre.simoesdiasvieira@arm.com> References: <20241002171339.299940-1-andre.simoesdiasvieira@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This patch splits out FCMA as a feature from Armv8.3-A and adds it as a separate feature bit which now controls 'TARGET_COMPLEX'. gcc/ChangeLog: * config/aarch64/aarch64-arches.def (FCMA): New feature bit, can not be used as an extension in the command-line. * config/aarch64/aarch64.h (TARGET_COMPLEX): Use FCMA feature bit rather than ARMV8_3. --- gcc/config/aarch64/aarch64-arches.def | 2 +- gcc/config/aarch64/aarch64-option-extensions.def | 1 + gcc/config/aarch64/aarch64.h | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/gcc/config/aarch64/aarch64-arches.def b/gcc/config/aarch64/aarch64-arches.def index 4634b272e28..fadf9c36b03 100644 --- a/gcc/config/aarch64/aarch64-arches.def +++ b/gcc/config/aarch64/aarch64-arches.def @@ -33,7 +33,7 @@ AARCH64_ARCH("armv8-a", generic_armv8_a, V8A, 8, (SIMD)) AARCH64_ARCH("armv8.1-a", generic_armv8_a, V8_1A, 8, (V8A, LSE, CRC, RDMA)) AARCH64_ARCH("armv8.2-a", generic_armv8_a, V8_2A, 8, (V8_1A)) -AARCH64_ARCH("armv8.3-a", generic_armv8_a, V8_3A, 8, (V8_2A, PAUTH, RCPC)) +AARCH64_ARCH("armv8.3-a", generic_armv8_a, V8_3A, 8, (V8_2A, PAUTH, RCPC, FCMA)) AARCH64_ARCH("armv8.4-a", generic_armv8_a, V8_4A, 8, (V8_3A, F16FML, DOTPROD, FLAGM)) AARCH64_ARCH("armv8.5-a", generic_armv8_a, V8_5A, 8, (V8_4A, SB, SSBS, PREDRES)) AARCH64_ARCH("armv8.6-a", generic_armv8_a, V8_6A, 8, (V8_5A, I8MM, BF16)) diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index 6998627f377..4732c20ec96 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -193,6 +193,7 @@ AARCH64_OPT_EXTENSION("sve2-sm4", SVE2_SM4, (SVE2, SM4), (), (), "svesm4") AARCH64_FMV_FEATURE("sve2-sm4", SVE_SM4, (SVE2_SM4)) AARCH64_OPT_FMV_EXTENSION("sme", SME, (BF16, SVE2), (), (), "sme") +AARCH64_OPT_EXTENSION("", FCMA, (), (), (), "fcma") AARCH64_OPT_EXTENSION("memtag", MEMTAG, (), (), (), "") diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index a99e7bb6c47..c0ad305e324 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -362,7 +362,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED #define TARGET_JSCVT (TARGET_FLOAT && TARGET_ARMV8_3) /* Armv8.3-a Complex number extension to AdvSIMD extensions. */ -#define TARGET_COMPLEX (TARGET_SIMD && TARGET_ARMV8_3) +#define TARGET_COMPLEX (TARGET_SIMD && AARCH64_HAVE_ISA (FCMA)) /* Floating-point rounding instructions from Armv8.5-a. */ #define TARGET_FRINT (AARCH64_HAVE_ISA (V8_5A) && TARGET_FLOAT)