From patchwork Wed Sep 18 03:27:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bohan Lei X-Patchwork-Id: 1986649 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.a=rsa-sha256 header.s=default header.b=ENWYHn2B; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X7kcb3NPXz1y20 for ; Wed, 18 Sep 2024 13:27:59 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6C9C33858C33 for ; Wed, 18 Sep 2024 03:27:57 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from out30-118.freemail.mail.aliyun.com (out30-118.freemail.mail.aliyun.com [115.124.30.118]) by sourceware.org (Postfix) with ESMTPS id 098423858D26 for ; Wed, 18 Sep 2024 03:27:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 098423858D26 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 098423858D26 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.118 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1726630057; cv=none; b=xH9NL3fbf/AMDWv6XZwrZvpfzL0cxzUHEoU+wqf8vrThopj/ATRVPNe98Xb2KR0ddq5miwex24tFbqC8X6wvCwxwf196rdJNTEfEqPRiZArLREDB9w+IBsngqnkOkKmADvn0AFPJAtVGKh+2MNWBKdFnMLddyxINr7mE2T8zhIg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1726630057; c=relaxed/simple; bh=iUI9N/BjceeE3fbNvs3n0NZ22ky4T2Ls3IaGQGzR85U=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=xI04CiIykypm011Dsjub1xQ05NMEKQLo/GmBiZJ8AB6CSPWvVVtoF/yVuRY0OKAu6Oaf95G+xBTs8zfgeeGMX37Cz452DUNZXD5kO5EsSMHkrFVC6TkXhCn0gv35Jntaws9m73Kw98gELtFrtkB7t1A2Ucp+wv8dyMvGCBREEdM= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1726630049; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=9mrmzGDe4/ayGjFHoJDQgDIvL+crrJigYvzoIckWOBg=; b=ENWYHn2BXbMm6bG5QzyNoTG14do1//m2ktLI6E2LF/wDBHyACUTsyamlemV6ONLoruXCDg26FMngnJBaYxxQGauvXBKR4CXvz8cfc+ecrNkF/kz3Q36sRRq7Y5K7ybn4xzL6qHWKRhlcA1xvfnToSQeGiFp/Xv6pXPM7FmA4LIQ= Received: from localhost(mailfrom:garthlei@linux.alibaba.com fp:SMTPD_---0WFCf861_1726630034) by smtp.aliyun-inc.com; Wed, 18 Sep 2024 11:27:24 +0800 From: Bohan Lei To: gcc-patches@gcc.gnu.org Cc: Bohan Lei Subject: [PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx Date: Wed, 18 Sep 2024 11:27:08 +0800 Message-Id: <20240918032708.14908-1-garthlei@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) MIME-Version: 1.0 X-Spam-Status: No, score=-28.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, UNPARSEABLE_RELAY, USER_IN_DEF_DKIM_WL, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org The RISC-V vector machine description relies on the helper function `sew64_scalar_helper` to emit actual insns for the DI variants of vssub.vx and vssubu.vx. This works with vssub.vx, but can cause problems with vssubu.vx with the scalar operand being constant zero, because `has_vi_variant_p` returns false, and the operand will be taken without being loaded into a reg. The attached testcases can cause an internal compiler error as a result. Allowing a constant zero operand in those insns seems to be a simple solution that only affects minimum existing code. gcc/ChangeLog: * config/riscv/vector.md: Allow zero operand for DI variants of vssubu.vx gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vssubu-1.c: New test. * gcc.target/riscv/rvv/base/vssubu-2.c: New test. --- gcc/config/riscv/vector.md | 8 ++++---- gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c | 11 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c | 11 +++++++++++ 3 files changed, 26 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index d0677325ba1..66a2a477faf 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -4400,10 +4400,10 @@ (define_insn "*pred__scalar" (sat_int_minus_binop:VI_D (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr") (vec_duplicate:VI_D - (match_operand: 4 "register_operand" " r, r, r, r"))) + (match_operand: 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))) (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" - "v.vx\t%0,%3,%4%p1" + "v.vx\t%0,%3,%z4%p1" [(set_attr "type" "") (set_attr "mode" "")]) @@ -4422,10 +4422,10 @@ (define_insn "*pred__extended_scalar" (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr") (vec_duplicate:VI_D (sign_extend: - (match_operand: 4 "register_operand" " r, r, r, r")))) + (match_operand: 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")))) (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR && !TARGET_64BIT" - "v.vx\t%0,%3,%4%p1" + "v.vx\t%0,%3,%z4%p1" [(set_attr "type" "") (set_attr "mode" "")]) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c new file mode 100644 index 00000000000..f19b42aed04 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gcv -mabi=lp64d" } */ + +#include + +vuint64m1_t test_vssubu_vx_u64m1(vuint64m1_t op1) +{ + return __riscv_vssubu_vx_u64m1(op1,0,0); +} + +/* { dg-final { scan-assembler-not {\tvssubu} } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c new file mode 100644 index 00000000000..cb4e4f48a9b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gcv -mabi=ilp32d" } */ + +#include + +vuint64m1_t test_vssubu_vx_u64m1(vuint64m1_t op1) +{ + return __riscv_vssubu_vx_u64m1(op1,0,0); +} + +/* { dg-final { scan-assembler-not {\tvssubu} } } */ \ No newline at end of file