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X-CSE-ConnectionGUID: ayS3QdvrTiiegZTEOXeSXw== X-CSE-MsgGUID: Vs3xkw07RFixsbTJDMHApg== X-IronPort-AV: E=McAfee;i="6700,10204,11193"; a="42578799" X-IronPort-AV: E=Sophos;i="6.10,224,1719903600"; d="scan'208";a="42578799" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Sep 2024 15:43:10 -0700 X-CSE-ConnectionGUID: IqqdbtGtTqaI1WbuBdW1TQ== X-CSE-MsgGUID: E4CaaVIUS5KW2kn3Y1+8kQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,224,1719903600"; d="scan'208";a="68636042" Received: from panli.sh.intel.com ([10.239.154.73]) by orviesa008.jf.intel.com with ESMTP; 12 Sep 2024 15:43:08 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, Tamar.Christina@arm.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v4 4/4] RISC-V: Fix vector SAT_ADD dump check due to middle-end change Date: Fri, 13 Sep 2024 06:42:12 +0800 Message-ID: <20240912224212.803040-1-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch would like fix the dump check times of vector SAT_ADD. The middle-end change makes the match times from 2 to 4 times. The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: Adjust the dump check times from 2 to 4. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: Ditto. Signed-off-by: Pan Li --- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c | 2 +- 16 files changed, 16 insertions(+), 16 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c index c525ba97c52..47dd5012cc6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_6(uint8_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c index 41372d08e52..df8d5a8d275 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_6(uint16_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c index dddebb54426..f286bd10e4b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_6(uint32_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c index ad5162d10a0..307ff36cc35 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_6(uint64_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c index 39c20b3cea6..3218962724c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_7(uint8_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c index 6eefaeebf31..922df02278d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_7(uint16_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c index 78beb1bd39e..7653f81531c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_7(uint32_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c index 369fa296d08..18803afd19a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_7(uint64_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c index e827cdd1657..e95d6f73c38 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_8(uint8_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c index af16f48e228..34e10236381 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_8(uint16_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c index 0a8eabfbad1..7fc5e73fe1d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_8(uint32_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c index 38cbdfbcf07..9684fdf37f7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_8(uint64_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c index fe8a5a8262d..96787fc15e2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_2(uint8_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c index 1aeb24eed0d..f155d7c47c7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_2(uint16_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c index 0d2b0e4ab80..5fdb67cc1ca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_2(uint32_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c index 168c269f75e..eee4d902fb5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_2(uint64_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */