From patchwork Wed Sep 11 06:29:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1983696 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=LLQY2Ggy; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X3W1k6VRGz1y1C for ; Wed, 11 Sep 2024 16:31:38 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 39F9C385840B for ; Wed, 11 Sep 2024 06:31:36 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by sourceware.org (Postfix) with ESMTPS id 3ED7A3858C98 for ; Wed, 11 Sep 2024 06:31:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3ED7A3858C98 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 3ED7A3858C98 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1726036270; cv=none; b=uLan4VcoC//AzpuZaHCcl8k+EaRi2He9YDHqkBv64Hz0x6vuVcZ16d+RWyo1Al75AOjchN+/C5nUcgwmNWLu6j3LBs2MtaqsKkjaZYEgpUtVx6LWj5lc8QfNY36jW64tuKSO4QiDo7n2WnTH8QL6Jbp8IYCdG+rZcRY2rjeFjKU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1726036270; c=relaxed/simple; bh=rcA1EWt5F62aer5+xGFEnNFPKaA4dT+DDtnxhMMy8bM=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=Cs+wpJ/X9m7yBSe23tSkmEzGDdXrjdBltIoE2ooix8PQ9osPpmE5/irA7fuBpUOdROGAswqlXxgay+DmchoR7jqEpg1YxZqEO6AnOgEamhZsmZ9nARUAusgdXs2MeGERoPdcWiu4sUG9Zu6/KC73ENNS9pXNbl/K6w0ngCNGOS8= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726036263; x=1757572263; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=rcA1EWt5F62aer5+xGFEnNFPKaA4dT+DDtnxhMMy8bM=; b=LLQY2GgypbqxmpG7B8G79IW+az3+2GVyLGkUTC/hYXc7ntrkb4KdBeAX UHoL8+4LnmNpx1/iu6kdBsvnUyu5vKMbqfb2LowS12+qpqsQyU/zr5T4i bSinAzVmXHpIELqEbUd7EoaEmLuPA2tI9o4PmhL6WToYDatK6/G2zoEp7 g8hbXZhZZwhGtItRVpNFMsYbl5XIAZZmea1/NnqKu36mIbg2f3n5trF69 PgLvw7VvbOMGcL9/zxqC9CuShasQriA7yUj30XY2KRPHHKKR2T8oxdEgK FVm5omqmlmq3ZgU1NWxrr6HYARm0fpiALM2JnSksAsNGI6gd70WQFChST w==; X-CSE-ConnectionGUID: Y0r3JmJlQ0aDjngA5zVpVQ== X-CSE-MsgGUID: LO/8Ai5BS5K9jzA5It/SKw== X-IronPort-AV: E=McAfee;i="6700,10204,11191"; a="25013731" X-IronPort-AV: E=Sophos;i="6.10,219,1719903600"; d="scan'208";a="25013731" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2024 23:30:55 -0700 X-CSE-ConnectionGUID: yJv5FkXTRHmoj7RzproSFQ== X-CSE-MsgGUID: lGNo0traQCei6zQBTXX+ZA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,219,1719903600"; d="scan'208";a="66974655" Received: from panli.sh.intel.com ([10.239.154.73]) by fmviesa007.fm.intel.com with ESMTP; 10 Sep 2024 23:30:38 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, Tamar.Christina@arm.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v3 1/5] Genmatch: Add control flow graph match for case 0 and case 1 Date: Wed, 11 Sep 2024 14:29:41 +0800 Message-ID: <20240911062945.3358247-1-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li The gen_phi_on_cond can only support below control flow for cond from day 1. Aka: +------+ | def | | ... | +-----+ | cond |------>| def | +------+ | ... | | +-----+ | | v | +-----+ | | PHI |<----------+ +-----+ Unfortunately, there will be more scenarios of control flow on PHI. For example as below: T __attribute__((noinline)) \ sat_s_add_##T##_fmt_3 (T x, T y) \ { \ T sum; \ bool overflow = __builtin_add_overflow (x, y, &sum); \ return overflow ? x < 0 ? MIN : MAX : sum; \ } DEF_SAT_S_ADD_FMT_3(int8_t, uint8_t, INT8_MIN, INT8_MAX) With expanded RTL like below. 3 │ 4 │ __attribute__((noinline)) 5 │ int8_t sat_s_add_int8_t_fmt_3 (int8_t x, int8_t y) 6 │ { 7 │ signed char _1; 8 │ signed char _2; 9 │ int8_t _3; 10 │ __complex__ signed char _6; 11 │ _Bool _8; 12 │ signed char _9; 13 │ signed char _10; 14 │ signed char _11; 15 │ 16 │ ;; basic block 2, loop depth 0 17 │ ;; pred: ENTRY 18 │ _6 = .ADD_OVERFLOW (x_4(D), y_5(D)); 19 │ _2 = IMAGPART_EXPR <_6>; 20 │ if (_2 != 0) 21 │ goto ; [50.00%] 22 │ else 23 │ goto ; [50.00%] 24 │ ;; succ: 4 25 │ ;; 3 26 │ 27 │ ;; basic block 3, loop depth 0 28 │ ;; pred: 2 29 │ _1 = REALPART_EXPR <_6>; 30 │ goto ; [100.00%] 31 │ ;; succ: 5 32 │ 33 │ ;; basic block 4, loop depth 0 34 │ ;; pred: 2 35 │ _8 = x_4(D) < 0; 36 │ _9 = (signed char) _8; 37 │ _10 = -_9; 38 │ _11 = _10 ^ 127; 39 │ ;; succ: 5 40 │ 41 │ ;; basic block 5, loop depth 0 42 │ ;; pred: 3 43 │ ;; 4 44 │ # _3 = PHI <_1(3), _11(4)> 45 │ return _3; 46 │ ;; succ: EXIT 47 │ 48 │ } The above code will have below control flow which is not supported by the gen_phi_on_cond. +------+ | def | | ... | +-----+ | cond |------>| def | +------+ | ... | | +-----+ | | v | +-----+ | | def | | | ... | | +-----+ | | | | | v | +-----+ | | PHI |<----------+ +-----+ This patch would like to add support above control flow matching for the gen_phi_on_cond. The below testsuites are passed for this patch: * The rv64gcv fully regression test. * The x86 bootstrap test. * The x86 fully regression test. gcc/ChangeLog: * gimple-match-head.cc (match_control_flow_graph_case_0): Add new func impl to match case 0 of cfg. (match_control_flow_graph_case_1): Ditto but for case 1. Signed-off-by: Pan Li --- gcc/gimple-match-head.cc | 115 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/gcc/gimple-match-head.cc b/gcc/gimple-match-head.cc index 924d3f1e710..c51728ae742 100644 --- a/gcc/gimple-match-head.cc +++ b/gcc/gimple-match-head.cc @@ -375,3 +375,118 @@ gimple_bitwise_inverted_equal_p (tree expr1, tree expr2, bool &wascmp, tree (*va return true; return false; } + +/* + * Return TRUE if the cfg matches the below layout by the given b2 in + * the first argument. Or return FALSE. + * + * If return TRUE, the output argument b_out will be updated to the b0 + * block as below example. + * + * If return FALSE, the output argument b_out will be NULL_BLOCK. + * + * | + * | + * v + * +------+ + * | b0: | + * | def | +-----+ + * | ... | | b1: | + * | cond |------>| def | + * +------+ | ... | + * | +-----+ + * | | + * v | + * +-----+ | + * | b2: | | + * | def |<----------+ + * +-----+ + */ +static inline bool +match_control_flow_graph_case_0 (basic_block b2, basic_block *b_out) +{ + *b_out = NULL; + + if (EDGE_COUNT (b2->preds) != 2) + return false; + + basic_block pred_0 = EDGE_PRED (b2, 0)->src; + basic_block pred_1 = EDGE_PRED (b2, 1)->src; + + if (pred_0 == NULL || pred_1 == NULL) + return false; + + if (!(EDGE_COUNT (pred_0->succs) == 2 && EDGE_COUNT (pred_1->succs) == 1) + && !(EDGE_COUNT (pred_0->succs) == 1 && EDGE_COUNT (pred_1->succs) == 2)) + return false; + + basic_block b0 = EDGE_COUNT (pred_0->succs) == 2 ? pred_0 : pred_1; + basic_block b1 = EDGE_COUNT (pred_0->succs) == 1 ? pred_0 : pred_1; + + if (EDGE_COUNT (b1->preds) != 1 || EDGE_PRED (b1, 0)->src != b0) + return false; + + *b_out = b0; + return true; +} + +/* + * Return TRUE if the cfg matches the below layout by the given b3 in + * the first argument. Or return FALSE. + * + * If return TRUE, the output argument b_out will be updated to the b0 + * block as below example. + * + * If return FALSE, the output argument b_out will be NULL. + * + * | + * | + * v + * +------+ + * | b0: | + * | ... | +-----+ + * | cond |------>| b2: | + * +------+ | ... | + * | +-----+ + * | | + * v | + * +-----+ | + * | b1: | | + * | ... | | + * +-----+ | + * | | + * | | + * v | + * +-----+ | + * | b3: |<----------+ + * | ... | + * +-----+ + */ +static inline bool +match_control_flow_graph_case_1 (basic_block b3, basic_block *b_out) +{ + *b_out = NULL; + + if (EDGE_COUNT (b3->preds) != 2) + return false; + + basic_block b1 = EDGE_PRED (b3, 0)->src; + basic_block b2 = EDGE_PRED (b3, 1)->src; + + if (b1 == NULL || b2 == NULL) + return false; + + if (EDGE_COUNT (b1->succs) != 1 + || EDGE_COUNT (b1->preds) != 1 + || EDGE_COUNT (b2->succs) != 1 + || EDGE_COUNT (b2->preds) != 1) + return false; + + basic_block b0 = EDGE_PRED (b1, 0)->src; + + if (EDGE_COUNT (b0->succs) != 2 || EDGE_PRED (b2, 0)->src != b0) + return false; + + *b_out = b0; + return true; +}