From patchwork Tue Sep 10 23:03:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1983577 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=eK+cNMyv; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X3K6Z3vFcz1y1y for ; Wed, 11 Sep 2024 09:05:09 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 871C9385B503 for ; Tue, 10 Sep 2024 23:05:07 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by sourceware.org (Postfix) with ESMTPS id 984D73858435 for ; Tue, 10 Sep 2024 23:04:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 984D73858435 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 984D73858435 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1726009486; cv=none; b=lvp/b5OvWjvSHHSvjAaMiBx6l/ygH6KpBv9cpMizeXIyznNoLcDfsfbJRT7omO8TxteYXLvEJBxT2yvkVN16oNBberFrMKCNHSHOchDtxgfLmZj1c02Mm4l9Je1k4HtqrW6VhY98OCSRfENMqGs3D/8mhRmyosjASETVVT3YVeQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1726009486; c=relaxed/simple; bh=+K3vb7LLZNrv6H0GYGw3X1FBTG+qefWf3/kWPtR+Ao8=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=k0hem7FSEZZt+SVZMOL5NOti/j+TzTUtLehPDrqBFbgof0cZorJ5jDBIHbF44tUGkX1UYlgqIwW6H93KBKoTAtC83Pd3lnToBtfV8m7MvVCHZpshTeZTOCqgHjzP+jadhyTXU1JL0vvM8HvFG6EPg++JMB4geZXw5lfW6CHSolo= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726009478; x=1757545478; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=+K3vb7LLZNrv6H0GYGw3X1FBTG+qefWf3/kWPtR+Ao8=; b=eK+cNMyvSNZ9szehL+yZDo7H0FDXEsfB0w7GsDmM6eFltbr6Zb37BBoe e5/H0KBnfzBWJLuqhBQxMgkhFioskXShOLxuR4m8tYvw33m9nmDC+51qN CE08XwE6exS5dyiY2OYYNCwwY9dFQANn9W7CdKqdoCy4n8TrM0cpy+Drt S77ccWwsMMMsKUj3v1vtRe8/zFI7O1W6rx2sovShzRAPVtj2SHpMONfYo JGOVrkz+aAcnJC8WL3CWfu8eFS1zwqPDSFur1DRu1Py42OfvLmR1P8bh1 dLFib6k6onX+EJ2lt9cVlfuqKHGBe2zxnl7S8K+cqtlnGdEodylBuLOxG g==; X-CSE-ConnectionGUID: VoeWYPDsSl2x4X7M4TLYzA== X-CSE-MsgGUID: NFnhUUrmTn2BbadiEUZLrA== X-IronPort-AV: E=McAfee;i="6700,10204,11191"; a="50198581" X-IronPort-AV: E=Sophos;i="6.10,218,1719903600"; d="scan'208";a="50198581" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2024 16:04:37 -0700 X-CSE-ConnectionGUID: JMPPuVD/TSKbqI40Wtj7ZA== X-CSE-MsgGUID: unynN1hyT+S8+ZosOaryPA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,218,1719903600"; d="scan'208";a="98011886" Received: from panli.sh.intel.com ([10.239.154.73]) by fmviesa001.fm.intel.com with ESMTP; 10 Sep 2024 16:04:35 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1] RISC-V: Fix asm check for Vector SAT_* due to middle-end change Date: Wed, 11 Sep 2024 07:03:42 +0800 Message-ID: <20240910230342.2564309-1-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li The middle-end change makes the effect on the layout of the assembly for vector SAT_*. This patch would like to fix it and make it robust. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Adjust asm check and make it robust. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c: Ditto. Signed-off-by: Pan Li Signed-off-by: Pan Li --- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c | 5 ++--- .../riscv/rvv/autovec/binop/vec_sat_u_add-10.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_add-11.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_add-12.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_add-13.c | 5 ++--- .../riscv/rvv/autovec/binop/vec_sat_u_add-14.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_add-15.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_add-16.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_add-17.c | 5 ++--- .../riscv/rvv/autovec/binop/vec_sat_u_add-18.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_add-19.c | 4 +--- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_add-20.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_add-21.c | 5 ++--- .../riscv/rvv/autovec/binop/vec_sat_u_add-22.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_add-23.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_add-24.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_add-25.c | 5 ++--- .../riscv/rvv/autovec/binop/vec_sat_u_add-26.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_add-27.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_add-28.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_add-29.c | 5 ++--- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_add-30.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_add-31.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_add-32.c | 4 +--- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c | 4 +--- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c | 5 ++--- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c | 4 +--- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c | 4 +--- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c | 4 +--- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c | 5 ++--- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c | 5 ++--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-10.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-11.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-12.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-13.c | 5 ++--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-14.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-15.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-16.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-17.c | 5 ++--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-18.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-19.c | 4 +--- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-20.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-21.c | 5 ++--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-22.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-23.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-24.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-25.c | 5 ++--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-26.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-27.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-28.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-29.c | 5 ++--- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-30.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-31.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-32.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-33.c | 5 ++--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-34.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-35.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-36.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-37.c | 5 ++--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-38.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-39.c | 4 +--- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c | 4 +--- .../riscv/rvv/autovec/binop/vec_sat_u_sub-40.c | 4 +--- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c | 5 ++--- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c | 4 +--- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c | 4 +--- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c | 4 +--- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c | 5 ++--- .../riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c | 5 +++-- .../riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c | 5 +++-- .../riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c | 5 +++-- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c | 5 ++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c | 5 ++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c | 7 ++++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c | 5 ++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c | 5 ++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c | 7 ++++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c | 9 ++++++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c | 5 ++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c | 7 ++++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c | 5 ++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c | 5 ++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c | 7 ++++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c | 7 ++++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c | 9 ++++++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c | 5 ++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c | 7 ++++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c | 5 ++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c | 9 ++++++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c | 5 ++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c | 7 ++++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c | 5 ++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c | 5 ++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c | 7 ++++--- .../riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c | 9 ++++++--- 99 files changed, 179 insertions(+), 294 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c index 348313b511f..d7d1dae010d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c @@ -8,9 +8,8 @@ /* ** vec_sat_u_add_uint8_t_fmt_1: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma +** ... ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c index 425d4c768d6..4397c10943a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint16_t_fmt_3: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma ** ... -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c index 903ae36e464..b93b582680f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint32_t_fmt_3: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** ... -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c index b9db496f2fa..ec3c6af4ee6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint64_t_fmt_3: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** ... -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c index 72d17c0a971..35f17c1b82d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c @@ -8,9 +8,8 @@ /* ** vec_sat_u_add_uint8_t_fmt_4: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma +** ... ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c index 1aa4fbe701f..11690843160 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint16_t_fmt_4: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma ** ... -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c index 664fa61d67c..9949047a6c7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint32_t_fmt_4: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** ... -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c index f752327e951..84c44f9a46b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint64_t_fmt_4: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** ... -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c index 352e22e56e5..5f61acbec0d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c @@ -8,9 +8,8 @@ /* ** vec_sat_u_add_uint8_t_fmt_5: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma +** ... ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c index 7a1996d38bc..eb4486ca765 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint16_t_fmt_5: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma ** ... -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c index c01c9f468a4..470eb6b3cfe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint32_t_fmt_5: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** ... -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c index e4f7c64331b..b381c05091a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint16_t_fmt_1: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma ** ... -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c index 66ca4cd2749..6bd2c30c139 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint64_t_fmt_5: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** ... -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c index 2e77b067cf3..c525ba97c52 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c @@ -8,9 +8,8 @@ /* ** vec_sat_u_add_uint8_t_fmt_6: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma +** ... ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c index 2e824049874..41372d08e52 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint16_t_fmt_6: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma ** ... -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c index 9283ce340b8..dddebb54426 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint32_t_fmt_6: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** ... -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c index fcf7c928140..ad5162d10a0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint64_t_fmt_6: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** ... -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c index a5ca9228a20..39c20b3cea6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c @@ -8,9 +8,8 @@ /* ** vec_sat_u_add_uint8_t_fmt_7: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma +** ... ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c index 9d379ae46a1..6eefaeebf31 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint16_t_fmt_7: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma ** ... -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c index 7b89fe1c3cf..78beb1bd39e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint32_t_fmt_7: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** ... -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c index f7c37df2888..369fa296d08 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint64_t_fmt_7: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** ... -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c index fbf57ff1642..e827cdd1657 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c @@ -8,9 +8,8 @@ /* ** vec_sat_u_add_uint8_t_fmt_8: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma +** ... ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c index a0847c90f3f..97a9b1fb973 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint32_t_fmt_1: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** ... -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c index e8b6de3ceb3..af16f48e228 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint16_t_fmt_8: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma ** ... -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c index 57f4bf2c427..0a8eabfbad1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint32_t_fmt_8: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** ... -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c index 47a3bc1c2f2..38cbdfbcf07 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint64_t_fmt_8: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** ... -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c index 3556761c430..8da2cb413d8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint64_t_fmt_1: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** ... -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c index c89ecea75cc..fe8a5a8262d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c @@ -8,9 +8,8 @@ /* ** vec_sat_u_add_uint8_t_fmt_2: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma +** ... ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c index 0f0f4542fb2..1aeb24eed0d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint16_t_fmt_2: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma ** ... -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c index e0e311d8b5b..0d2b0e4ab80 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint32_t_fmt_2: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** ... -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c index b76b231c06e..168c269f75e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_add_uint64_t_fmt_2: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** ... -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c index b13ff0aad8b..d636302842c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c @@ -8,9 +8,8 @@ /* ** vec_sat_u_add_uint8_t_fmt_3: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma +** ... ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c index f0ce17d1959..5d214301727 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c @@ -8,9 +8,8 @@ /* ** vec_sat_u_sub_uint8_t_fmt_1: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma +** ... ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c index fac941945e9..e50121bd031 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint16_t_fmt_3: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma ** ... -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c index 0c6afc391b4..de460c176a2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint32_t_fmt_3: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** ... -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c index 41fe3b86deb..96e06f0c6be 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint64_t_fmt_3: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** ... -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c index a52e38a7ed2..dffe957629a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c @@ -8,9 +8,8 @@ /* ** vec_sat_u_sub_uint8_t_fmt_4: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma +** ... ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c index 1ee8391d883..97b2e17e74a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint16_t_fmt_4: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma ** ... -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c index d74a9822431..978c37ca138 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint32_t_fmt_4: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** ... -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c index 70284382fba..f43c5711eca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint64_t_fmt_4: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** ... -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c index d44514cdb97..f435b6e0831 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c @@ -8,9 +8,8 @@ /* ** vec_sat_u_sub_uint8_t_fmt_5: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma +** ... ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c index 5dbbf202b1f..74fe1e31804 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint16_t_fmt_5: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma ** ... -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c index 4696753b903..b83b87b2b1b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint32_t_fmt_5: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** ... -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c index c73413a4597..549970684fa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint16_t_fmt_1: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma ** ... -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c index b963ba1e1e1..0ae3c37a783 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint64_t_fmt_5: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** ... -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c index fc2682bd24f..e16a0d22cbb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c @@ -8,9 +8,8 @@ /* ** vec_sat_u_sub_uint8_t_fmt_6: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma +** ... ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c index 4e51e4aa7f8..6b4bc69c005 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint16_t_fmt_6: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma ** ... -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c index b16925ebac3..6be7c7669de 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint32_t_fmt_6: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** ... -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c index 9d99a4ea71c..e9eb157fb9d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint64_t_fmt_6: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** ... -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c index 424551e1500..4980789dcd4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c @@ -8,9 +8,8 @@ /* ** vec_sat_u_sub_uint8_t_fmt_7: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma +** ... ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c index 110318824d8..2a4d1cc93e7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint16_t_fmt_7: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma ** ... -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c index 981c0713c18..8c14d9a2c01 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint32_t_fmt_7: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** ... -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c index 15915372713..32d3a62d303 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint64_t_fmt_7: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** ... -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c index 9c971f6a3d1..8c098ac336a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c @@ -8,9 +8,8 @@ /* ** vec_sat_u_sub_uint8_t_fmt_8: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma +** ... ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c index 447b6814b8a..2af04851e04 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint32_t_fmt_1: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** ... -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c index 09bcd0d3468..4a4fc746326 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint16_t_fmt_8: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma ** ... -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c index 704f560b79a..5c912a32549 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint32_t_fmt_8: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** ... -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c index 8011f6c19cc..50aa0ae59d7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint64_t_fmt_8: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** ... -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c index 2a5727677ed..329dd230b02 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c @@ -8,9 +8,8 @@ /* ** vec_sat_u_sub_uint8_t_fmt_9: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma +** ... ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c index 4a7d7e55c9f..a024eadc2a7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint16_t_fmt_9: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma ** ... -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c index cfad5d787e3..56216e97620 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint32_t_fmt_9: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** ... -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c index 721fd27a288..707bfd2e1c6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint64_t_fmt_9: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** ... -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c index 1e3b5e7bf3e..e7dc212fe52 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c @@ -8,9 +8,8 @@ /* ** vec_sat_u_sub_uint8_t_fmt_10: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma +** ... ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c index 4bc3205dc30..b814830da32 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint16_t_fmt_10: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma ** ... -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c index 3ec28cd3fc7..e6c6aaac800 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint32_t_fmt_10: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** ... -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c index 5eca3debeaf..21727fb3a43 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint64_t_fmt_1: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** ... -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c index 656c35cc22a..716e58e8ae3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint64_t_fmt_10: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** ... -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c index 942d2e91acc..e1d78aff28c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c @@ -8,9 +8,8 @@ /* ** vec_sat_u_sub_uint8_t_fmt_2: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma +** ... ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c index c27fc4d5331..9911cbcfb37 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint16_t_fmt_2: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma ** ... -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c index 817435955a5..8c83af1fc67 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint32_t_fmt_2: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** ... -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c index 42cf16f13b0..d76d754b721 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c @@ -8,10 +8,8 @@ /* ** vec_sat_u_sub_uint64_t_fmt_2: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** ... -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c index 9eb26d9f52c..3b6b53274f2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c @@ -8,9 +8,8 @@ /* ** vec_sat_u_sub_uint8_t_fmt_3: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma +** ... ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c index ab2287032d6..792d8a02877 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c @@ -8,11 +8,12 @@ /* ** vec_sat_u_sub_trunc_uint8_t_fmt_1: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma ** ... -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+ +** ... ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma +** ... ** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c index 2c752e72258..67780360ce1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c @@ -8,11 +8,12 @@ /* ** vec_sat_u_sub_trunc_uint16_t_fmt_1: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** ... -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+ +** ... ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma +** ... ** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c index 7f89d7099b0..04f2d0b2d95 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c @@ -8,11 +8,12 @@ /* ** vec_sat_u_sub_trunc_uint32_t_fmt_1: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** ... -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+ +** ... ** vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma +** ... ** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c index ae3e44cd57e..60ab5382fa9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c @@ -8,10 +8,9 @@ /* ** vec_sat_u_trunc_uint8_t_uint16_t_fmt_1: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint16_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c index f5084e503eb..2566450445f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c @@ -8,10 +8,9 @@ /* ** vec_sat_u_trunc_uint16_t_uint32_t_fmt_2: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_2 (uint16_t, uint32_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c index e2ab880a1ac..f90432bb903 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c @@ -8,12 +8,13 @@ /* ** vec_sat_u_trunc_uint16_t_uint64_t_fmt_2: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 +** ... ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_2 (uint16_t, uint64_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c index e996c9442dd..5330e19c679 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c @@ -8,10 +8,9 @@ /* ** vec_sat_u_trunc_uint32_t_uint64_t_fmt_2: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_2 (uint32_t, uint64_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c index 49bdbdc3606..45d74eab2cd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c @@ -8,10 +8,9 @@ /* ** vec_sat_u_trunc_uint8_t_uint16_t_fmt_3: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint16_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c index 3ff696edcfe..c9ce8788274 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c @@ -8,12 +8,13 @@ /* ** vec_sat_u_trunc_uint8_t_uint32_t_fmt_3: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 +** ... ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint32_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c index 7fca4a43fd3..5529c710f92 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c @@ -8,14 +8,17 @@ /* ** vec_sat_u_trunc_uint8_t_uint64_t_fmt_3: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 +** ... ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 +** ... ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint64_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c index 201fcaa4f69..6d773e96da3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c @@ -8,10 +8,9 @@ /* ** vec_sat_u_trunc_uint16_t_uint32_t_fmt_3: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_3 (uint16_t, uint32_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c index 99a9600102c..808f62bff10 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c @@ -8,12 +8,13 @@ /* ** vec_sat_u_trunc_uint16_t_uint64_t_fmt_3: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 +** ... ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_3 (uint16_t, uint64_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c index f1bd5400f6b..12a0e2ff380 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c @@ -8,10 +8,9 @@ /* ** vec_sat_u_trunc_uint32_t_uint64_t_fmt_3: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_3 (uint32_t, uint64_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c index a80cefe46ab..9c7979d326c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c @@ -8,10 +8,9 @@ /* ** vec_sat_u_trunc_uint8_t_uint16_t_fmt_4: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint16_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c index 2516468fd16..cf6f404f65e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c @@ -8,12 +8,13 @@ /* ** vec_sat_u_trunc_uint8_t_uint32_t_fmt_1: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 +** ... ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint32_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c index 9a4d261d052..2e497b7ec1c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c @@ -8,12 +8,13 @@ /* ** vec_sat_u_trunc_uint8_t_uint32_t_fmt_4: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 +** ... ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint32_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c index 5f0b71be834..dd996d21c5e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c @@ -8,14 +8,17 @@ /* ** vec_sat_u_trunc_uint8_t_uint64_t_fmt_4: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 +** ... ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 +** ... ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint64_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c index 059758b8bb3..a6c125408ce 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c @@ -8,10 +8,9 @@ /* ** vec_sat_u_trunc_uint16_t_uint32_t_fmt_4: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_4 (uint16_t, uint32_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c index 6e094d07111..2551b2f5a05 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c @@ -8,12 +8,13 @@ /* ** vec_sat_u_trunc_uint16_t_uint64_t_fmt_4: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 +** ... ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_4 (uint16_t, uint64_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c index 707b20b0e01..bfcfa805e19 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c @@ -8,10 +8,9 @@ /* ** vec_sat_u_trunc_uint32_t_uint64_t_fmt_4: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_4 (uint32_t, uint64_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c index 5df05f72cbb..787c5644bb0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c @@ -8,14 +8,17 @@ /* ** vec_sat_u_trunc_uint8_t_uint64_t_fmt_1: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 +** ... ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 +** ... ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint64_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c index 89dd65374a5..b236c2a2caf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c @@ -8,10 +8,9 @@ /* ** vec_sat_u_trunc_uint16_t_uint32_t_fmt_1: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_1 (uint16_t, uint32_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c index 851a20e5037..1747585c59e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c @@ -8,12 +8,13 @@ /* ** vec_sat_u_trunc_uint16_t_uint64_t_fmt_1: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 +** ... ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_1 (uint16_t, uint64_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c index 8ae3bc243cd..fd30184b1de 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c @@ -8,10 +8,9 @@ /* ** vec_sat_u_trunc_uint32_t_uint64_t_fmt_1: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_1 (uint32_t, uint64_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c index a5b566b6d80..dc9bbb5fe96 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c @@ -8,10 +8,9 @@ /* ** vec_sat_u_trunc_uint8_t_uint16_t_fmt_2: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma -** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint16_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c index a6df321057e..0525b8f5159 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c @@ -8,12 +8,13 @@ /* ** vec_sat_u_trunc_uint8_t_uint32_t_fmt_2: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 +** ... ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint32_t) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c index 7c68825213f..96621231999 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c @@ -8,14 +8,17 @@ /* ** vec_sat_u_trunc_uint8_t_uint64_t_fmt_2: ** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 +** ... ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 +** ... ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma +** ... ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) ** ... */ DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint64_t)