From patchwork Tue Sep 10 05:56:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jin Ma X-Patchwork-Id: 1982959 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.a=rsa-sha256 header.s=default header.b=ArbUkXqd; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X2tJp13Bhz1y1C for ; Tue, 10 Sep 2024 15:57:30 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 53DE0385DDD4 for ; Tue, 10 Sep 2024 05:57:25 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from out30-112.freemail.mail.aliyun.com (out30-112.freemail.mail.aliyun.com [115.124.30.112]) by sourceware.org (Postfix) with ESMTPS id 4E0993858C53 for ; Tue, 10 Sep 2024 05:57:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4E0993858C53 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4E0993858C53 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.112 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1725947827; cv=none; b=SaJVfgRfDi+xxyxhtwgKJaoZup99JoKpX4u7nDrgp8MS1oEgktdAiN/n5IdEHPX4mRfhepPgju8aF1TFVUseOjE0cjPPDvuXItyYq9NL9AOX5g5ERXRfNZ+eVS8HdMSyTEYJhz6LwOQEkJB+E0DNXl0hERUWJ3P8d8weydsWCus= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1725947827; c=relaxed/simple; bh=3DQePzWR5ddR4m7Q2NwFSZdiQf8pUmAXlR5u7EVdFhU=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=H1/u5evlNMZBz18bpMTqqXftEF06kLlkrHST0jjEKpmhVCYOUUFYwMPs+6rIwcrHq/pSSCGKxBG6DuKPcKgefCZh+FqlCKONOqQXKii0uNcORvR68lL0rXTNmer+Wm74rZyXWRuJV0LWXlhqMxtNG115unLh0a3Q8MjtiWWtx9E= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1725947821; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=BA8vWjGgWAlApDSiTeAKIL/lvSXjNSk1wm2FMjbPqLk=; b=ArbUkXqdx8Y2hta7/7nrJz2RbjKwByzfDNDHcptLUbERg8FtYar4910l1dBBS2jBO1dAQh5ySnqf++1mOxdweeY+TsHolSw1EHtDUqK4wg/oZ5S6NMIb62U7YmkxavdsxOl+KFjzFYWOHvfMaaLu6t/uVgyAJ/hNcFSc3sOHNJI= Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0WEj4QBW_1725947818) by smtp.aliyun-inc.com; Tue, 10 Sep 2024 13:56:59 +0800 From: Jin Ma To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, juzhe.zhong@rivai.ai, pan2.li@intel.com, kito.cheng@gmail.com, richard.guenther@gmail.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH v2 2/2] RISC-V: Fix ICE due to inconsistency of RVV intrinsic list in lto and cc1. Date: Tue, 10 Sep 2024 13:56:47 +0800 Message-Id: <20240910055647.634-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20240906173047.306-1-jinma@linux.alibaba.com> References: <20240906173047.306-1-jinma@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-27.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, UNPARSEABLE_RELAY, URIBL_SBL_A, USER_IN_DEF_DKIM_WL, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org When we use flto, the function list of rvv will be generated twice, once in the cc1 phase and once in the lto phase. However, due to the different generation methods, the two lists are different. For example, when there is no zvfh or zvfhmin in arch, it is generated by calling function "riscv_pragma_intrinsic". since the TARGET_VECTOR_ELEN_FP_16 is enabled before rvv function generation, a list of rvv functions related to float16 will be generated. In the lto phase, the rvv function list is generated only by calling the function "riscv_init_builtins", but the TARGET_VECTOR_ELEN_FP_16 is disabled, so that the float16-related rvv function list cannot be generated like cc1. This will cause confusion, resulting in matching tothe wrong function due to inconsistent fcode in the lto phase, eventually leading to ICE. So I think we should be consistent with their generated lists, which is exactly what this patch does. gcc/ChangeLog: * config/riscv/riscv-c.cc (struct pragma_intrinsic_flags): Mov to riscv-protos.h. (riscv_pragma_intrinsic_flags_pollute): Mov to riscv-vector-builtins.c. (riscv_pragma_intrinsic_flags_restore): Likewise. (riscv_pragma_intrinsic): Likewise. * config/riscv/riscv-protos.h (struct pragma_intrinsic_flags): New. (riscv_pragma_intrinsic_flags_restore): New. (riscv_pragma_intrinsic_flags_pollute): New. * config/riscv/riscv-vector-builtins.cc (riscv_pragma_intrinsic_flags_pollute): New. (riscv_pragma_intrinsic_flags_restore): New. (handle_pragma_vector_for_lto): New. (init_builtins): Correct the processing logic for lto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/bug-11.c: New test. --- gcc/config/riscv/riscv-c.cc | 70 +------------------ gcc/config/riscv/riscv-protos.h | 13 ++++ gcc/config/riscv/riscv-vector-builtins.cc | 83 ++++++++++++++++++++++- 3 files changed, 96 insertions(+), 70 deletions(-) diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index 71112d9c66d7..7037ecc1268a 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -34,72 +34,6 @@ along with GCC; see the file COPYING3. If not see #define builtin_define(TXT) cpp_define (pfile, TXT) -struct pragma_intrinsic_flags -{ - int intrinsic_target_flags; - - int intrinsic_riscv_vector_elen_flags; - int intrinsic_riscv_zvl_flags; - int intrinsic_riscv_zvb_subext; - int intrinsic_riscv_zvk_subext; -}; - -static void -riscv_pragma_intrinsic_flags_pollute (struct pragma_intrinsic_flags *flags) -{ - flags->intrinsic_target_flags = target_flags; - flags->intrinsic_riscv_vector_elen_flags = riscv_vector_elen_flags; - flags->intrinsic_riscv_zvl_flags = riscv_zvl_flags; - flags->intrinsic_riscv_zvb_subext = riscv_zvb_subext; - flags->intrinsic_riscv_zvk_subext = riscv_zvk_subext; - - target_flags = target_flags - | MASK_VECTOR; - - riscv_zvl_flags = riscv_zvl_flags - | MASK_ZVL32B - | MASK_ZVL64B - | MASK_ZVL128B; - - riscv_vector_elen_flags = riscv_vector_elen_flags - | MASK_VECTOR_ELEN_32 - | MASK_VECTOR_ELEN_64 - | MASK_VECTOR_ELEN_FP_16 - | MASK_VECTOR_ELEN_FP_32 - | MASK_VECTOR_ELEN_FP_64; - - riscv_zvb_subext = riscv_zvb_subext - | MASK_ZVBB - | MASK_ZVBC - | MASK_ZVKB; - - riscv_zvk_subext = riscv_zvk_subext - | MASK_ZVKG - | MASK_ZVKNED - | MASK_ZVKNHA - | MASK_ZVKNHB - | MASK_ZVKSED - | MASK_ZVKSH - | MASK_ZVKN - | MASK_ZVKNC - | MASK_ZVKNG - | MASK_ZVKS - | MASK_ZVKSC - | MASK_ZVKSG - | MASK_ZVKT; -} - -static void -riscv_pragma_intrinsic_flags_restore (struct pragma_intrinsic_flags *flags) -{ - target_flags = flags->intrinsic_target_flags; - - riscv_vector_elen_flags = flags->intrinsic_riscv_vector_elen_flags; - riscv_zvl_flags = flags->intrinsic_riscv_zvl_flags; - riscv_zvb_subext = flags->intrinsic_riscv_zvb_subext; - riscv_zvk_subext = flags->intrinsic_riscv_zvk_subext; -} - static int riscv_ext_version_value (unsigned major, unsigned minor) { @@ -269,14 +203,14 @@ riscv_pragma_intrinsic (cpp_reader *) { struct pragma_intrinsic_flags backup_flags; - riscv_pragma_intrinsic_flags_pollute (&backup_flags); + riscv_vector::riscv_pragma_intrinsic_flags_pollute (&backup_flags); riscv_option_override (); init_adjust_machine_modes (); riscv_vector::reinit_builtins (); riscv_vector::handle_pragma_vector (); - riscv_pragma_intrinsic_flags_restore (&backup_flags); + riscv_vector::riscv_pragma_intrinsic_flags_restore (&backup_flags); /* Re-initialize after the flags are restored. */ riscv_option_override (); diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 3358e3887b95..651df2310da6 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -102,6 +102,15 @@ struct riscv_address_info { int shift; }; +struct pragma_intrinsic_flags +{ + int intrinsic_target_flags; + int intrinsic_riscv_vector_elen_flags; + int intrinsic_riscv_zvl_flags; + int intrinsic_riscv_zvb_subext; + int intrinsic_riscv_zvk_subext; +}; + /* Routines implemented in riscv.cc. */ extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p); extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx); @@ -569,6 +578,10 @@ enum avl_type VLS = 2, }; /* Routines implemented in riscv-vector-builtins.cc. */ +void +riscv_pragma_intrinsic_flags_restore (struct pragma_intrinsic_flags *); +void +riscv_pragma_intrinsic_flags_pollute (struct pragma_intrinsic_flags *); void init_builtins (void); void reinit_builtins (void); const char *mangle_builtin_type (const_tree); diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 0176670fbdf2..421c40be3ba5 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -4510,6 +4510,83 @@ builtin_type_p (const_tree type) return lookup_vector_type_attribute (type); } +void +riscv_pragma_intrinsic_flags_pollute (struct pragma_intrinsic_flags *flags) +{ + flags->intrinsic_target_flags = target_flags; + flags->intrinsic_riscv_vector_elen_flags = riscv_vector_elen_flags; + flags->intrinsic_riscv_zvl_flags = riscv_zvl_flags; + flags->intrinsic_riscv_zvb_subext = riscv_zvb_subext; + flags->intrinsic_riscv_zvk_subext = riscv_zvk_subext; + + target_flags = target_flags + | MASK_VECTOR; + + riscv_zvl_flags = riscv_zvl_flags + | MASK_ZVL32B + | MASK_ZVL64B + | MASK_ZVL128B; + + riscv_vector_elen_flags = riscv_vector_elen_flags + | MASK_VECTOR_ELEN_32 + | MASK_VECTOR_ELEN_64 + | MASK_VECTOR_ELEN_FP_16 + | MASK_VECTOR_ELEN_FP_32 + | MASK_VECTOR_ELEN_FP_64; + + riscv_zvb_subext = riscv_zvb_subext + | MASK_ZVBB + | MASK_ZVBC + | MASK_ZVKB; + + riscv_zvk_subext = riscv_zvk_subext + | MASK_ZVKG + | MASK_ZVKNED + | MASK_ZVKNHA + | MASK_ZVKNHB + | MASK_ZVKSED + | MASK_ZVKSH + | MASK_ZVKN + | MASK_ZVKNC + | MASK_ZVKNG + | MASK_ZVKS + | MASK_ZVKSC + | MASK_ZVKSG + | MASK_ZVKT; +} + +void +riscv_pragma_intrinsic_flags_restore (struct pragma_intrinsic_flags *flags) +{ + target_flags = flags->intrinsic_target_flags; + + riscv_vector_elen_flags = flags->intrinsic_riscv_vector_elen_flags; + riscv_zvl_flags = flags->intrinsic_riscv_zvl_flags; + riscv_zvb_subext = flags->intrinsic_riscv_zvb_subext; + riscv_zvk_subext = flags->intrinsic_riscv_zvk_subext; +} + +/* Helper for init_builtins in LTO. */ +static void +handle_pragma_vector_for_lto () +{ + struct pragma_intrinsic_flags backup_flags; + + riscv_pragma_intrinsic_flags_pollute (&backup_flags); + + riscv_option_override (); + init_adjust_machine_modes (); + + register_builtin_types (); + + handle_pragma_vector (); + riscv_pragma_intrinsic_flags_restore (&backup_flags); + + /* Re-initialize after the flags are restored. */ + riscv_option_override (); + init_adjust_machine_modes (); +} + /* Initialize all compiler built-ins related to RVV that should be defined at start-up. */ void @@ -4518,9 +4595,11 @@ init_builtins () rvv_switcher rvv; if (!TARGET_VECTOR) return; - register_builtin_types (); + if (in_lto_p) - handle_pragma_vector (); + handle_pragma_vector_for_lto (); + else + register_builtin_types (); } /* Reinitialize builtins similar to init_builtins, but only the null