From patchwork Wed Sep 4 13:26:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 1980826 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=L1tya0dW; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WzNrg38gxz1yXY for ; Wed, 4 Sep 2024 23:39:31 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3FC26384AB44 for ; Wed, 4 Sep 2024 13:39:29 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-oo1-xc35.google.com (mail-oo1-xc35.google.com [IPv6:2607:f8b0:4864:20::c35]) by sourceware.org (Postfix) with ESMTPS id 22D18385DDCF for ; Wed, 4 Sep 2024 13:27:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 22D18385DDCF Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 22D18385DDCF Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::c35 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1725456480; cv=none; b=xp3m0ptIY7i2b9BmkivEH5cKmiq+KZLY49NaGtSlIcSWIXJI3qpKQ5O6YXhrSUAN6oP8IDyFzezImxJiAejlZ7DWNPih1XghA4oPHyy71UTtCWtJ7OTkFlKcltVZIq8YHm3+wQ9Mo/lJDsD/sijb/3M06pa+94rGtLLvFayFNc4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1725456480; c=relaxed/simple; bh=h5ihID5OsjLz4Bfem+23BCtf/VEV4VGGUpXM0zWltBA=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=AnlGIlOlQHL8mWoWoFoM0hZ659AzcfTlXgDE3mFRzc9IETiRruKi1Z4ErPH5WCNe0ezauFtBjdb9U3bChJ03ZJjHoB2Viy1f1FYcXVhCtBgnvKWrcYj4UWrKf2LriqxrEvqt0cr5xiKWYKz5JNXCFM6f/xJeXupPBEFfm1Rxf5Q= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-oo1-xc35.google.com with SMTP id 006d021491bc7-5dcd8403656so4650955eaf.1 for ; Wed, 04 Sep 2024 06:27:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1725456476; x=1726061276; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZRg+ayUp0X5pN/YPpTrZ8MQmKY5XoA7J9gtDmtFPYEc=; b=L1tya0dW1c4F83grQbX8kBW4Myn/cWj9yETfrdyz2B4vKIikkN74k/FIfbSc19h9hL BXHnk4tLvBAf9KwozKkLW6aRwa14yDPtDm5E1XZs2MK+9Zb0TfVxQTF04GtnovQb1uRy zVPrZYIsKgwzt++1PJPAHnxm2lsS166q+qUjaRyLwr2frNUSMoHEh+1sEwG9kXfnFs0W lTmaJ3jXgEJzQaI3314yLFklpdXnhrSSKQr8u8D/7wOemuDaA8PveG+BB1OngWq+BK+r y45+oevkPSDY+jC9whXGI2tcq9luia+wqx18K/0Lb3q3fO8cf/QxWlxZ12Ko3R4fAOdG nfeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725456476; x=1726061276; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZRg+ayUp0X5pN/YPpTrZ8MQmKY5XoA7J9gtDmtFPYEc=; b=QnayNemEY10LLAz44DdovPq8WJz7v6fp+thqH9XU3gZ4vXCUZBa+OO2M8saCL7r47G 03vTHMGLCLRgfXCxsX6HBnoD8z9xXGbyDSABmyXoIXrneYIqBLumvdgfIWZEXCt7RC9B lB2Cj+45pGOSoCGkKJd70ZHVHuqgrNlrcbHmhJJX15o9E+wdK1iizH2T2LR7eT8vjPa3 bikXFvzlwvFeofU7iD1Gp2PVOGyJjmNAENnb3PiAc8zEgpbiP1Oun2n0LaPFCnzgsbPw Rfp3OWvwyXNLfAq0dXbEbkGvKThDVvMxM6Dgg5a+M7PfybizUOH6CnKYBVWFeTapPCZc Es7w== X-Gm-Message-State: AOJu0YyPwRs7KvuXRNu2K1qCZNScAnbED3qL+Nq6kIagd6EK4gye9LKO voF/E92EVaSe2cvExMkEHJ0leaeNbS37Rqz83mAh3LE6NL4I0mnjMoGdPsmLD+GHBs3N2YzNqzS fl/9nCQ== X-Google-Smtp-Source: AGHT+IErCv/XCuorHBkItIySmiLZRKPjjm3IA3RDPRHSQGkFifJMyGQLXU2uzmxVM5YNJoSvDR9lhg== X-Received: by 2002:a05:6820:2216:b0:5d6:ae6:a852 with SMTP id 006d021491bc7-5dfacf28289mr22295167eaf.6.1725456471990; Wed, 04 Sep 2024 06:27:51 -0700 (PDT) Received: from localhost.localdomain ([139.178.84.207]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5dfa0580692sm2308062eaf.46.2024.09.04.06.27.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2024 06:27:51 -0700 (PDT) From: Christophe Lyon To: gcc-patches@gcc.gnu.org, richard.earnshaw@arm.com, ramanara@nvidia.com Cc: Christophe Lyon Subject: [PATCH v2 34/36] arm: [MVE intrinsics] rework vadcq Date: Wed, 4 Sep 2024 13:26:48 +0000 Message-Id: <20240904132650.2720446-35-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240904132650.2720446-1-christophe.lyon@linaro.org> References: <20240711214305.3193022-1-christophe.lyon@linaro.org> <20240904132650.2720446-1-christophe.lyon@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Implement vadcq using the new MVE builtins framework. We re-use most of the code introduced by the previous patch to support vadciq: we just need to initialize carry from the input parameter. 2024-08-28 Christophe Lyon gcc/ * config/arm/arm-mve-builtins-base.cc (vadcq_vsbc): Add support for vadcq. * config/arm/arm-mve-builtins-base.def (vadcq): New. * config/arm/arm-mve-builtins-base.h (vadcq): New. * config/arm/arm_mve.h (vadcq): Delete. (vadcq_m): Delete. (vadcq_s32): Delete. (vadcq_u32): Delete. (vadcq_m_s32): Delete. (vadcq_m_u32): Delete. (__arm_vadcq_s32): Delete. (__arm_vadcq_u32): Delete. (__arm_vadcq_m_s32): Delete. (__arm_vadcq_m_u32): Delete. (__arm_vadcq): Delete. (__arm_vadcq_m): Delete. --- gcc/config/arm/arm-mve-builtins-base.cc | 61 +++++++++++++++-- gcc/config/arm/arm-mve-builtins-base.def | 1 + gcc/config/arm/arm-mve-builtins-base.h | 1 + gcc/config/arm/arm_mve.h | 87 ------------------------ 4 files changed, 56 insertions(+), 94 deletions(-) diff --git a/gcc/config/arm/arm-mve-builtins-base.cc b/gcc/config/arm/arm-mve-builtins-base.cc index 6f3b18c2915..9c2e11356ef 100644 --- a/gcc/config/arm/arm-mve-builtins-base.cc +++ b/gcc/config/arm/arm-mve-builtins-base.cc @@ -559,10 +559,19 @@ public: class vadc_vsbc_impl : public function_base { public: + CONSTEXPR vadc_vsbc_impl (bool init_carry) + : m_init_carry (init_carry) + {} + + /* Initialize carry with 0 (vadci). */ + bool m_init_carry; + unsigned int call_properties (const function_instance &) const override { unsigned int flags = CP_WRITE_MEMORY | CP_READ_FPCR; + if (!m_init_carry) + flags |= CP_READ_MEMORY; return flags; } @@ -605,22 +614,59 @@ public: carry_ptr = e.args[carry_out_arg_no]; e.args.ordered_remove (carry_out_arg_no); + if (!m_init_carry) + { + /* Prepare carry in: + set_fpscr ( (fpscr & ~0x20000000u) + | ((*carry & 1u) << 29) ) */ + rtx carry_in = gen_reg_rtx (SImode); + rtx fpscr = gen_reg_rtx (SImode); + emit_insn (gen_get_fpscr_nzcvqc (fpscr)); + emit_insn (gen_rtx_SET (carry_in, gen_rtx_MEM (SImode, carry_ptr))); + + emit_insn (gen_rtx_SET (carry_in, + gen_rtx_ASHIFT (SImode, + carry_in, + GEN_INT (29)))); + emit_insn (gen_rtx_SET (carry_in, + gen_rtx_AND (SImode, + carry_in, + GEN_INT (0x20000000)))); + emit_insn (gen_rtx_SET (fpscr, + gen_rtx_AND (SImode, + fpscr, + GEN_INT (~0x20000000)))); + emit_insn (gen_rtx_SET (carry_in, + gen_rtx_IOR (SImode, + carry_in, + fpscr))); + emit_insn (gen_set_fpscr_nzcvqc (carry_in)); + } + switch (e.pred) { case PRED_none: /* No predicate. */ - unspec = e.type_suffix (0).unsigned_p - ? VADCIQ_U - : VADCIQ_S; + unspec = m_init_carry + ? (e.type_suffix (0).unsigned_p + ? VADCIQ_U + : VADCIQ_S) + : (e.type_suffix (0).unsigned_p + ? VADCQ_U + : VADCQ_S); code = code_for_mve_q_v4si (unspec, unspec); insns = e.use_exact_insn (code); break; case PRED_m: /* "m" predicate. */ - unspec = e.type_suffix (0).unsigned_p - ? VADCIQ_M_U - : VADCIQ_M_S; + unspec = m_init_carry + ? (e.type_suffix (0).unsigned_p + ? VADCIQ_M_U + : VADCIQ_M_S) + : (e.type_suffix (0).unsigned_p + ? VADCQ_M_U + : VADCQ_M_S); code = code_for_mve_q_m_v4si (unspec, unspec); insns = e.use_cond_insn (code, 0); break; @@ -816,7 +862,8 @@ namespace arm_mve { FUNCTION_PRED_P_S_U (vabavq, VABAVQ) FUNCTION_WITHOUT_N (vabdq, VABDQ) FUNCTION (vabsq, unspec_based_mve_function_exact_insn, (ABS, ABS, ABS, -1, -1, -1, VABSQ_M_S, -1, VABSQ_M_F, -1, -1, -1)) -FUNCTION (vadciq, vadc_vsbc_impl,) +FUNCTION (vadciq, vadc_vsbc_impl, (true)) +FUNCTION (vadcq, vadc_vsbc_impl, (false)) FUNCTION_WITH_RTX_M_N (vaddq, PLUS, VADDQ) FUNCTION_PRED_P_S_U (vaddlvaq, VADDLVAQ) FUNCTION_PRED_P_S_U (vaddlvq, VADDLVQ) diff --git a/gcc/config/arm/arm-mve-builtins-base.def b/gcc/config/arm/arm-mve-builtins-base.def index 72d6461c4e4..37efa6bf13e 100644 --- a/gcc/config/arm/arm-mve-builtins-base.def +++ b/gcc/config/arm/arm-mve-builtins-base.def @@ -22,6 +22,7 @@ DEF_MVE_FUNCTION (vabavq, binary_acca_int32, all_integer, p_or_none) DEF_MVE_FUNCTION (vabdq, binary, all_integer, mx_or_none) DEF_MVE_FUNCTION (vabsq, unary, all_signed, mx_or_none) DEF_MVE_FUNCTION (vadciq, vadc_vsbc, integer_32, m_or_none) +DEF_MVE_FUNCTION (vadcq, vadc_vsbc, integer_32, m_or_none) DEF_MVE_FUNCTION (vaddlvaq, unary_widen_acc, integer_32, p_or_none) DEF_MVE_FUNCTION (vaddlvq, unary_acc, integer_32, p_or_none) DEF_MVE_FUNCTION (vaddq, binary_opt_n, all_integer, mx_or_none) diff --git a/gcc/config/arm/arm-mve-builtins-base.h b/gcc/config/arm/arm-mve-builtins-base.h index 2dfc2e18062..eb8423c3fe2 100644 --- a/gcc/config/arm/arm-mve-builtins-base.h +++ b/gcc/config/arm/arm-mve-builtins-base.h @@ -27,6 +27,7 @@ extern const function_base *const vabavq; extern const function_base *const vabdq; extern const function_base *const vabsq; extern const function_base *const vadciq; +extern const function_base *const vadcq; extern const function_base *const vaddlvaq; extern const function_base *const vaddlvq; extern const function_base *const vaddq; diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 3a0b3041c42..dd7b6f5cdab 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -85,8 +85,6 @@ #define vstrdq_scatter_base_wb_p(__addr, __offset, __value, __p) __arm_vstrdq_scatter_base_wb_p(__addr, __offset, __value, __p) #define vstrwq_scatter_base_wb_p(__addr, __offset, __value, __p) __arm_vstrwq_scatter_base_wb_p(__addr, __offset, __value, __p) #define vstrwq_scatter_base_wb(__addr, __offset, __value) __arm_vstrwq_scatter_base_wb(__addr, __offset, __value) -#define vadcq(__a, __b, __carry) __arm_vadcq(__a, __b, __carry) -#define vadcq_m(__inactive, __a, __b, __carry, __p) __arm_vadcq_m(__inactive, __a, __b, __carry, __p) #define vsbciq(__a, __b, __carry_out) __arm_vsbciq(__a, __b, __carry_out) #define vsbciq_m(__inactive, __a, __b, __carry_out, __p) __arm_vsbciq_m(__inactive, __a, __b, __carry_out, __p) #define vsbcq(__a, __b, __carry) __arm_vsbcq(__a, __b, __carry) @@ -319,10 +317,6 @@ #define vstrwq_scatter_base_wb_s32(__addr, __offset, __value) __arm_vstrwq_scatter_base_wb_s32(__addr, __offset, __value) #define vstrwq_scatter_base_wb_u32(__addr, __offset, __value) __arm_vstrwq_scatter_base_wb_u32(__addr, __offset, __value) #define vstrwq_scatter_base_wb_f32(__addr, __offset, __value) __arm_vstrwq_scatter_base_wb_f32(__addr, __offset, __value) -#define vadcq_s32(__a, __b, __carry) __arm_vadcq_s32(__a, __b, __carry) -#define vadcq_u32(__a, __b, __carry) __arm_vadcq_u32(__a, __b, __carry) -#define vadcq_m_s32(__inactive, __a, __b, __carry, __p) __arm_vadcq_m_s32(__inactive, __a, __b, __carry, __p) -#define vadcq_m_u32(__inactive, __a, __b, __carry, __p) __arm_vadcq_m_u32(__inactive, __a, __b, __carry, __p) #define vsbciq_s32(__a, __b, __carry_out) __arm_vsbciq_s32(__a, __b, __carry_out) #define vsbciq_u32(__a, __b, __carry_out) __arm_vsbciq_u32(__a, __b, __carry_out) #define vsbciq_m_s32(__inactive, __a, __b, __carry_out, __p) __arm_vsbciq_m_s32(__inactive, __a, __b, __carry_out, __p) @@ -1684,46 +1678,6 @@ __arm_vstrwq_scatter_base_wb_u32 (uint32x4_t * __addr, const int __offset, uint3 *__addr = __builtin_mve_vstrwq_scatter_base_wb_uv4si (*__addr, __offset, __value); } -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vadcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry) -{ - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); - int32x4_t __res = __builtin_mve_vadcq_sv4si (__a, __b); - *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; - return __res; -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vadcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry) -{ - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); - uint32x4_t __res = __builtin_mve_vadcq_uv4si (__a, __b); - *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; - return __res; -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vadcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, unsigned * __carry, mve_pred16_t __p) -{ - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); - int32x4_t __res = __builtin_mve_vadcq_m_sv4si (__inactive, __a, __b, __p); - *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; - return __res; -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vadcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, unsigned * __carry, mve_pred16_t __p) -{ - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); - uint32x4_t __res = __builtin_mve_vadcq_m_uv4si (__inactive, __a, __b, __p); - *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; - return __res; -} - __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsbciq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry_out) @@ -3600,34 +3554,6 @@ __arm_vstrwq_scatter_base_wb (uint32x4_t * __addr, const int __offset, uint32x4_ __arm_vstrwq_scatter_base_wb_u32 (__addr, __offset, __value); } -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vadcq (int32x4_t __a, int32x4_t __b, unsigned * __carry) -{ - return __arm_vadcq_s32 (__a, __b, __carry); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vadcq (uint32x4_t __a, uint32x4_t __b, unsigned * __carry) -{ - return __arm_vadcq_u32 (__a, __b, __carry); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vadcq_m (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, unsigned * __carry, mve_pred16_t __p) -{ - return __arm_vadcq_m_s32 (__inactive, __a, __b, __carry, __p); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vadcq_m (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, unsigned * __carry, mve_pred16_t __p) -{ - return __arm_vadcq_m_u32 (__inactive, __a, __b, __carry, __p); -} - __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsbciq (int32x4_t __a, int32x4_t __b, unsigned * __carry_out) @@ -5245,19 +5171,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1, p2), \ int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1, p2))) -#define __arm_vadcq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vadcq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3, p4), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vadcq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3, p4));}) - -#define __arm_vadcq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vadcq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vadcq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) - #define __arm_vsbciq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \