diff mbox series

[v2,32/36] arm: [MVE intrinsics] factorize vadc vadci vsbc vsbci

Message ID 20240904132650.2720446-33-christophe.lyon@linaro.org
State New
Headers show
Series arm: [MVE intrinsics] Re-implement more intrinsics | expand

Commit Message

Christophe Lyon Sept. 4, 2024, 1:26 p.m. UTC 
Factorize vadc/vsbc and vadci/vsbci so that they use the same
parameterized names.

2024-08-28  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/
	* config/arm/iterators.md (mve_insn): Add VADCIQ_M_S, VADCIQ_M_U,
	VADCIQ_U, VADCIQ_S, VADCQ_M_S, VADCQ_M_U, VADCQ_S, VADCQ_U,
	VSBCIQ_M_S, VSBCIQ_M_U, VSBCIQ_S, VSBCIQ_U, VSBCQ_M_S, VSBCQ_M_U,
	VSBCQ_S, VSBCQ_U.
	(VADCIQ, VSBCIQ): Merge into ...
	(VxCIQ): ... this.
	(VADCIQ_M, VSBCIQ_M): Merge into ...
	(VxCIQ_M): ... this.
	(VSBCQ, VADCQ): Merge into ...
	(VxCQ): ... this.
	(VSBCQ_M, VADCQ_M): Merge into ...
	(VxCQ_M): ... this.
	* config/arm/mve.md
	(mve_vadciq_<supf>v4si, mve_vsbciq_<supf>v4si): Merge into ...
	(@mve_<mve_insn>q_<supf>v4si): ... this.
	(mve_vadciq_m_<supf>v4si, mve_vsbciq_m_<supf>v4si): Merge into ...
	(@mve_<mve_insn>q_m_<supf>v4si): ... this.
	(mve_vadcq_<supf>v4si, mve_vsbcq_<supf>v4si): Merge into ...
	(@mve_<mve_insn>q_<supf>v4si): ... this.
	(mve_vadcq_m_<supf>v4si, mve_vsbcq_m_<supf>v4si): Merge into ...
	(@mve_<mve_insn>q_m_<supf>v4si): ... this.
---
 gcc/config/arm/iterators.md |  20 +++---
 gcc/config/arm/mve.md       | 131 +++++++++---------------------------
 2 files changed, 42 insertions(+), 109 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 2fb3b25040f..59e112b228c 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -941,6 +941,10 @@  (define_int_attr mve_insn [
 		 (VABDQ_S "vabd") (VABDQ_U "vabd") (VABDQ_F "vabd")
 		 (VABSQ_M_F "vabs")
 		 (VABSQ_M_S "vabs")
+		 (VADCIQ_M_S "vadci") (VADCIQ_M_U "vadci")
+		 (VADCIQ_S "vadci") (VADCIQ_U "vadci")
+		 (VADCQ_M_S "vadc") (VADCQ_M_U "vadc")
+		 (VADCQ_S "vadc") (VADCQ_U "vadc")
 		 (VADDLVAQ_P_S "vaddlva") (VADDLVAQ_P_U "vaddlva")
 		 (VADDLVAQ_S "vaddlva") (VADDLVAQ_U "vaddlva")
 		 (VADDLVQ_P_S "vaddlv") (VADDLVQ_P_U "vaddlv")
@@ -1235,6 +1239,10 @@  (define_int_attr mve_insn [
 		 (VRSHRNTQ_N_S "vrshrnt") (VRSHRNTQ_N_U "vrshrnt")
 		 (VRSHRQ_M_N_S "vrshr") (VRSHRQ_M_N_U "vrshr")
 		 (VRSHRQ_N_S "vrshr") (VRSHRQ_N_U "vrshr")
+		 (VSBCIQ_M_S "vsbci") (VSBCIQ_M_U "vsbci")
+		 (VSBCIQ_S "vsbci") (VSBCIQ_U "vsbci")
+		 (VSBCQ_M_S "vsbc") (VSBCQ_M_U "vsbc")
+		 (VSBCQ_S "vsbc") (VSBCQ_U "vsbc")
 		 (VSHLLBQ_M_N_S "vshllb") (VSHLLBQ_M_N_U "vshllb")
 		 (VSHLLBQ_N_S "vshllb") (VSHLLBQ_N_U "vshllb")
 		 (VSHLLTQ_M_N_S "vshllt") (VSHLLTQ_M_N_U "vshllt")
@@ -2949,14 +2957,10 @@  (define_int_iterator VSTRWSBWBQ [VSTRWQSBWB_S VSTRWQSBWB_U])
 (define_int_iterator VLDRWGBWBQ [VLDRWQGBWB_S VLDRWQGBWB_U])
 (define_int_iterator VSTRDSBWBQ [VSTRDQSBWB_S VSTRDQSBWB_U])
 (define_int_iterator VLDRDGBWBQ [VLDRDQGBWB_S VLDRDQGBWB_U])
-(define_int_iterator VADCIQ [VADCIQ_U VADCIQ_S])
-(define_int_iterator VADCIQ_M [VADCIQ_M_U VADCIQ_M_S])
-(define_int_iterator VSBCQ [VSBCQ_U VSBCQ_S])
-(define_int_iterator VSBCQ_M [VSBCQ_M_U VSBCQ_M_S])
-(define_int_iterator VSBCIQ [VSBCIQ_U VSBCIQ_S])
-(define_int_iterator VSBCIQ_M [VSBCIQ_M_U VSBCIQ_M_S])
-(define_int_iterator VADCQ [VADCQ_U VADCQ_S])
-(define_int_iterator VADCQ_M [VADCQ_M_U VADCQ_M_S])
+(define_int_iterator VxCIQ [VADCIQ_U VADCIQ_S VSBCIQ_U VSBCIQ_S])
+(define_int_iterator VxCIQ_M [VADCIQ_M_U VADCIQ_M_S VSBCIQ_M_U VSBCIQ_M_S])
+(define_int_iterator VxCQ [VADCQ_U VADCQ_S  VSBCQ_U VSBCQ_S])
+(define_int_iterator VxCQ_M [VADCQ_M_U VADCQ_M_S  VSBCQ_M_U VSBCQ_M_S])
 (define_int_iterator UQRSHLLQ [UQRSHLL_64 UQRSHLL_48])
 (define_int_iterator SQRSHRLQ [SQRSHRL_64 SQRSHRL_48])
 (define_int_iterator VSHLCQ_M [VSHLCQ_M_S VSHLCQ_M_U])
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index eb603b3d9a7..9c32d0e1033 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -5717,159 +5717,88 @@  (define_insn "mve_vldrdq_gather_base_wb_z_<supf>v2di_insn"
 }
  [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrdq_gather_base_wb_<supf>v2di_insn"))
   (set_attr "length" "8")])
-;;
-;; [vadciq_m_s, vadciq_m_u])
-;;
-(define_insn "mve_vadciq_m_<supf>v4si"
-  [(set (match_operand:V4SI 0 "s_register_operand" "=w")
-	(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0")
-		      (match_operand:V4SI 2 "s_register_operand" "w")
-		      (match_operand:V4SI 3 "s_register_operand" "w")
-		      (match_operand:V4BI 4 "vpr_register_operand" "Up")]
-	 VADCIQ_M))
-   (set (reg:SI VFPCC_REGNUM)
-	(unspec:SI [(const_int 0)]
-	 VADCIQ_M))
-  ]
-  "TARGET_HAVE_MVE"
-  "vpst\;vadcit.i32\t%q0, %q2, %q3"
- [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vadciq_<supf>v4si"))
-  (set_attr "type" "mve_move")
-   (set_attr "length" "8")])
 
 ;;
-;; [vadciq_u, vadciq_s])
+;; [vadciq_u, vadciq_s]
+;; [vsbciq_s, vsbciq_u]
 ;;
-(define_insn "mve_vadciq_<supf>v4si"
+(define_insn "@mve_<mve_insn>q_<supf>v4si"
   [(set (match_operand:V4SI 0 "s_register_operand" "=w")
 	(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
 		      (match_operand:V4SI 2 "s_register_operand" "w")]
-	 VADCIQ))
+	 VxCIQ))
    (set (reg:SI VFPCC_REGNUM)
 	(unspec:SI [(const_int 0)]
-	 VADCIQ))
+	 VxCIQ))
   ]
   "TARGET_HAVE_MVE"
-  "vadci.i32\t%q0, %q1, %q2"
- [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vadciq_<supf>v4si"))
+  "<mve_insn>.i32\t%q0, %q1, %q2"
+ [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_<supf>v4si"))
   (set_attr "type" "mve_move")
    (set_attr "length" "4")])
 
 ;;
-;; [vadcq_m_s, vadcq_m_u])
+;; [vadciq_m_s, vadciq_m_u]
+;; [vsbciq_m_u, vsbciq_m_s]
 ;;
-(define_insn "mve_vadcq_m_<supf>v4si"
+(define_insn "@mve_<mve_insn>q_m_<supf>v4si"
   [(set (match_operand:V4SI 0 "s_register_operand" "=w")
 	(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0")
 		      (match_operand:V4SI 2 "s_register_operand" "w")
 		      (match_operand:V4SI 3 "s_register_operand" "w")
 		      (match_operand:V4BI 4 "vpr_register_operand" "Up")]
-	 VADCQ_M))
+	 VxCIQ_M))
    (set (reg:SI VFPCC_REGNUM)
-	(unspec:SI [(reg:SI VFPCC_REGNUM)]
-	 VADCQ_M))
+	(unspec:SI [(const_int 0)]
+	 VxCIQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vadct.i32\t%q0, %q2, %q3"
- [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vadcq_<supf>v4si"))
+  "vpst\;<mve_insn>t.i32\t%q0, %q2, %q3"
+ [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_<supf>v4si"))
   (set_attr "type" "mve_move")
    (set_attr "length" "8")])
 
 ;;
-;; [vadcq_u, vadcq_s])
+;; [vadcq_u, vadcq_s]
+;; [vsbcq_s, vsbcq_u]
 ;;
-(define_insn "mve_vadcq_<supf>v4si"
+(define_insn "@mve_<mve_insn>q_<supf>v4si"
   [(set (match_operand:V4SI 0 "s_register_operand" "=w")
 	(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
 		       (match_operand:V4SI 2 "s_register_operand" "w")]
-	 VADCQ))
+	 VxCQ))
    (set (reg:SI VFPCC_REGNUM)
 	(unspec:SI [(reg:SI VFPCC_REGNUM)]
-	 VADCQ))
+	 VxCQ))
   ]
   "TARGET_HAVE_MVE"
-  "vadc.i32\t%q0, %q1, %q2"
- [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vadcq_<supf>v4si"))
+  "<mve_insn>.i32\t%q0, %q1, %q2"
+ [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_<supf>v4si"))
   (set_attr "type" "mve_move")
    (set_attr "length" "4")
    (set_attr "conds" "set")])
 
 ;;
-;; [vsbciq_m_u, vsbciq_m_s])
+;; [vadcq_m_s, vadcq_m_u]
+;; [vsbcq_m_u, vsbcq_m_s]
 ;;
-(define_insn "mve_vsbciq_m_<supf>v4si"
+(define_insn "@mve_<mve_insn>q_m_<supf>v4si"
   [(set (match_operand:V4SI 0 "s_register_operand" "=w")
-	(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
-		      (match_operand:V4SI 2 "s_register_operand" "w")
-		      (match_operand:V4SI 3 "s_register_operand" "w")
-		      (match_operand:V4BI 4 "vpr_register_operand" "Up")]
-	 VSBCIQ_M))
-   (set (reg:SI VFPCC_REGNUM)
-	(unspec:SI [(const_int 0)]
-	 VSBCIQ_M))
-  ]
-  "TARGET_HAVE_MVE"
-  "vpst\;vsbcit.i32\t%q0, %q2, %q3"
- [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vsbciq_<supf>v4si"))
-  (set_attr "type" "mve_move")
-   (set_attr "length" "8")])
-
-;;
-;; [vsbciq_s, vsbciq_u])
-;;
-(define_insn "mve_vsbciq_<supf>v4si"
-  [(set (match_operand:V4SI 0 "s_register_operand" "=w")
-	(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
-		      (match_operand:V4SI 2 "s_register_operand" "w")]
-	 VSBCIQ))
-   (set (reg:SI VFPCC_REGNUM)
-	(unspec:SI [(const_int 0)]
-	 VSBCIQ))
-  ]
-  "TARGET_HAVE_MVE"
-  "vsbci.i32\t%q0, %q1, %q2"
- [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vsbciq_<supf>v4si"))
-  (set_attr "type" "mve_move")
-   (set_attr "length" "4")])
-
-;;
-;; [vsbcq_m_u, vsbcq_m_s])
-;;
-(define_insn "mve_vsbcq_m_<supf>v4si"
-  [(set (match_operand:V4SI 0 "s_register_operand" "=w")
-	(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
+	(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0")
 		      (match_operand:V4SI 2 "s_register_operand" "w")
 		      (match_operand:V4SI 3 "s_register_operand" "w")
 		      (match_operand:V4BI 4 "vpr_register_operand" "Up")]
-	 VSBCQ_M))
+	 VxCQ_M))
    (set (reg:SI VFPCC_REGNUM)
 	(unspec:SI [(reg:SI VFPCC_REGNUM)]
-	 VSBCQ_M))
+	 VxCQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vsbct.i32\t%q0, %q2, %q3"
- [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vsbcq_<supf>v4si"))
+  "vpst\;<mve_insn>t.i32\t%q0, %q2, %q3"
+ [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_<supf>v4si"))
   (set_attr "type" "mve_move")
    (set_attr "length" "8")])
 
-;;
-;; [vsbcq_s, vsbcq_u])
-;;
-(define_insn "mve_vsbcq_<supf>v4si"
-  [(set (match_operand:V4SI 0 "s_register_operand" "=w")
-	(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
-		      (match_operand:V4SI 2 "s_register_operand" "w")]
-	 VSBCQ))
-   (set (reg:SI VFPCC_REGNUM)
-	(unspec:SI [(reg:SI VFPCC_REGNUM)]
-	 VSBCQ))
-  ]
-  "TARGET_HAVE_MVE"
-  "vsbc.i32\t%q0, %q1, %q2"
- [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vsbcq_<supf>v4si"))
-  (set_attr "type" "mve_move")
-   (set_attr "length" "4")])
-
 ;;
 ;; [vst2q])
 ;;