| Message ID | 20240904132650.2720446-31-christophe.lyon@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | arm: [MVE intrinsics] Re-implement more intrinsics | expand |
On 04/09/2024 14:26, Christophe Lyon wrote: > Since we rewrote the implementation of vshlcq intrinsics, we no longer > need these expanders. > > 2024-08-28 Christophe Lyon <christophe.lyon@linaro.org> > > gcc/ > * config/arm/arm-builtins.cc > (arm_ternop_unone_none_unone_imm_qualifiers) > (-arm_ternop_none_none_unone_imm_qualifiers): Delete. > * config/arm/arm_mve_builtins.def (vshlcq_m_vec_s) > (vshlcq_m_carry_s, vshlcq_m_vec_u, vshlcq_m_carry_u): Delete. > * config/arm/mve.md (mve_vshlcq_vec_<supf><mode>): Delete. > (mve_vshlcq_carry_<supf><mode>): Delete. > (mve_vshlcq_m_vec_<supf><mode>): Delete. > (mve_vshlcq_m_carry_<supf><mode>): Delete. OK. R. > --- > gcc/config/arm/arm-builtins.cc | 13 ------- > gcc/config/arm/arm_mve_builtins.def | 8 ---- > gcc/config/arm/mve.md | 60 ----------------------------- > 3 files changed, 81 deletions(-) > > diff --git a/gcc/config/arm/arm-builtins.cc b/gcc/config/arm/arm-builtins.cc > index 697b91911dd..621fffec6d3 100644 > --- a/gcc/config/arm/arm-builtins.cc > +++ b/gcc/config/arm/arm-builtins.cc > @@ -476,19 +476,6 @@ arm_ternop_unone_unone_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] > #define TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS \ > (arm_ternop_unone_unone_none_none_qualifiers) > > -static enum arm_type_qualifiers > -arm_ternop_unone_none_unone_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] > - = { qualifier_unsigned, qualifier_none, qualifier_unsigned, > - qualifier_immediate }; > -#define TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS \ > - (arm_ternop_unone_none_unone_imm_qualifiers) > - > -static enum arm_type_qualifiers > -arm_ternop_none_none_unone_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] > - = { qualifier_none, qualifier_none, qualifier_unsigned, qualifier_immediate }; > -#define TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS \ > - (arm_ternop_none_none_unone_imm_qualifiers) > - > static enum arm_type_qualifiers > arm_ternop_unone_unone_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_unsigned, qualifier_unsigned, qualifier_none, > diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def > index f6962cd8cf5..9cce644858d 100644 > --- a/gcc/config/arm/arm_mve_builtins.def > +++ b/gcc/config/arm/arm_mve_builtins.def > @@ -288,15 +288,11 @@ VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrmlaldavhaq_u, v4si) > VAR2 (TERNOP_NONE_NONE_UNONE_PRED, vcvtq_m_to_f_u, v8hf, v4sf) > VAR2 (TERNOP_NONE_NONE_NONE_PRED, vcvtq_m_to_f_s, v8hf, v4sf) > VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_f, v8hf, v4sf) > -VAR3 (TERNOP_UNONE_NONE_UNONE_IMM, vshlcq_carry_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vshlcq_carry_u, v16qi, v8hi, v4si) > VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqrshrunbq_n_s, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_NONE_NONE, vabavq_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vabavq_u, v16qi, v8hi, v4si) > VAR2 (TERNOP_UNONE_UNONE_NONE_PRED, vcvtaq_m_u, v8hi, v4si) > VAR2 (TERNOP_NONE_NONE_NONE_PRED, vcvtaq_m_s, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vshlcq_vec_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_NONE_NONE_UNONE_IMM, vshlcq_vec_s, v16qi, v8hi, v4si) > VAR4 (TERNOP_UNONE_UNONE_UNONE_PRED, vpselq_u, v16qi, v8hi, v4si, v2di) > VAR4 (TERNOP_NONE_NONE_NONE_PRED, vpselq_s, v16qi, v8hi, v4si, v2di) > VAR3 (TERNOP_UNONE_UNONE_UNONE_PRED, vrev64q_m_u, v16qi, v8hi, v4si) > @@ -862,7 +858,3 @@ VAR1 (UQSHL, urshr_, si) > VAR1 (UQSHL, urshrl_, di) > VAR1 (UQSHL, uqshl_, si) > VAR1 (UQSHL, uqshll_, di) > -VAR3 (QUADOP_NONE_NONE_UNONE_IMM_PRED, vshlcq_m_vec_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_UNONE_IMM_PRED, vshlcq_m_carry_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlcq_m_vec_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlcq_m_carry_u, v16qi, v8hi, v4si) > diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md > index 83a1eb48533..eb603b3d9a7 100644 > --- a/gcc/config/arm/mve.md > +++ b/gcc/config/arm/mve.md > @@ -1691,34 +1691,6 @@ (define_insn "@mve_<mve_insn>q_<supf><mode>" > ;; > ;; [vshlcq_u vshlcq_s] > ;; > -(define_expand "mve_vshlcq_vec_<supf><mode>" > - [(match_operand:MVE_2 0 "s_register_operand") > - (match_operand:MVE_2 1 "s_register_operand") > - (match_operand:SI 2 "s_register_operand") > - (match_operand:SI 3 "mve_imm_32") > - (unspec:MVE_2 [(const_int 0)] VSHLCQ)] > - "TARGET_HAVE_MVE" > -{ > - rtx ignore_wb = gen_reg_rtx (SImode); > - emit_insn(gen_mve_vshlcq_<supf><mode>(operands[0], ignore_wb, operands[1], > - operands[2], operands[3])); > - DONE; > -}) > - > -(define_expand "mve_vshlcq_carry_<supf><mode>" > - [(match_operand:SI 0 "s_register_operand") > - (match_operand:MVE_2 1 "s_register_operand") > - (match_operand:SI 2 "s_register_operand") > - (match_operand:SI 3 "mve_imm_32") > - (unspec:MVE_2 [(const_int 0)] VSHLCQ)] > - "TARGET_HAVE_MVE" > -{ > - rtx ignore_vec = gen_reg_rtx (<MODE>mode); > - emit_insn(gen_mve_vshlcq_<supf><mode>(ignore_vec, operands[0], operands[1], > - operands[2], operands[3])); > - DONE; > -}) > - > (define_insn "@mve_vshlcq_<supf><mode>" > [(set (match_operand:MVE_2 0 "s_register_operand" "=w") > (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0") > @@ -6247,38 +6219,6 @@ (define_insn "mve_sqshll_di" > ;; > ;; [vshlcq_m_u vshlcq_m_s] > ;; > -(define_expand "mve_vshlcq_m_vec_<supf><mode>" > - [(match_operand:MVE_2 0 "s_register_operand") > - (match_operand:MVE_2 1 "s_register_operand") > - (match_operand:SI 2 "s_register_operand") > - (match_operand:SI 3 "mve_imm_32") > - (match_operand:<MVE_VPRED> 4 "vpr_register_operand") > - (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)] > - "TARGET_HAVE_MVE" > -{ > - rtx ignore_wb = gen_reg_rtx (SImode); > - emit_insn (gen_mve_vshlcq_m_<supf><mode> (operands[0], ignore_wb, operands[1], > - operands[2], operands[3], > - operands[4])); > - DONE; > -}) > - > -(define_expand "mve_vshlcq_m_carry_<supf><mode>" > - [(match_operand:SI 0 "s_register_operand") > - (match_operand:MVE_2 1 "s_register_operand") > - (match_operand:SI 2 "s_register_operand") > - (match_operand:SI 3 "mve_imm_32") > - (match_operand:<MVE_VPRED> 4 "vpr_register_operand") > - (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)] > - "TARGET_HAVE_MVE" > -{ > - rtx ignore_vec = gen_reg_rtx (<MODE>mode); > - emit_insn (gen_mve_vshlcq_m_<supf><mode> (ignore_vec, operands[0], > - operands[1], operands[2], > - operands[3], operands[4])); > - DONE; > -}) > - > (define_insn "@mve_vshlcq_m_<supf><mode>" > [(set (match_operand:MVE_2 0 "s_register_operand" "=w") > (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")
diff --git a/gcc/config/arm/arm-builtins.cc b/gcc/config/arm/arm-builtins.cc index 697b91911dd..621fffec6d3 100644 --- a/gcc/config/arm/arm-builtins.cc +++ b/gcc/config/arm/arm-builtins.cc @@ -476,19 +476,6 @@ arm_ternop_unone_unone_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS \ (arm_ternop_unone_unone_none_none_qualifiers) -static enum arm_type_qualifiers -arm_ternop_unone_none_unone_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] - = { qualifier_unsigned, qualifier_none, qualifier_unsigned, - qualifier_immediate }; -#define TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS \ - (arm_ternop_unone_none_unone_imm_qualifiers) - -static enum arm_type_qualifiers -arm_ternop_none_none_unone_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] - = { qualifier_none, qualifier_none, qualifier_unsigned, qualifier_immediate }; -#define TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS \ - (arm_ternop_none_none_unone_imm_qualifiers) - static enum arm_type_qualifiers arm_ternop_unone_unone_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned, qualifier_none, diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index f6962cd8cf5..9cce644858d 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -288,15 +288,11 @@ VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrmlaldavhaq_u, v4si) VAR2 (TERNOP_NONE_NONE_UNONE_PRED, vcvtq_m_to_f_u, v8hf, v4sf) VAR2 (TERNOP_NONE_NONE_NONE_PRED, vcvtq_m_to_f_s, v8hf, v4sf) VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_f, v8hf, v4sf) -VAR3 (TERNOP_UNONE_NONE_UNONE_IMM, vshlcq_carry_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vshlcq_carry_u, v16qi, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqrshrunbq_n_s, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_NONE_NONE, vabavq_s, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vabavq_u, v16qi, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_NONE_PRED, vcvtaq_m_u, v8hi, v4si) VAR2 (TERNOP_NONE_NONE_NONE_PRED, vcvtaq_m_s, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vshlcq_vec_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_NONE_NONE_UNONE_IMM, vshlcq_vec_s, v16qi, v8hi, v4si) VAR4 (TERNOP_UNONE_UNONE_UNONE_PRED, vpselq_u, v16qi, v8hi, v4si, v2di) VAR4 (TERNOP_NONE_NONE_NONE_PRED, vpselq_s, v16qi, v8hi, v4si, v2di) VAR3 (TERNOP_UNONE_UNONE_UNONE_PRED, vrev64q_m_u, v16qi, v8hi, v4si) @@ -862,7 +858,3 @@ VAR1 (UQSHL, urshr_, si) VAR1 (UQSHL, urshrl_, di) VAR1 (UQSHL, uqshl_, si) VAR1 (UQSHL, uqshll_, di) -VAR3 (QUADOP_NONE_NONE_UNONE_IMM_PRED, vshlcq_m_vec_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_UNONE_IMM_PRED, vshlcq_m_carry_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlcq_m_vec_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlcq_m_carry_u, v16qi, v8hi, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 83a1eb48533..eb603b3d9a7 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -1691,34 +1691,6 @@ (define_insn "@mve_<mve_insn>q_<supf><mode>" ;; ;; [vshlcq_u vshlcq_s] ;; -(define_expand "mve_vshlcq_vec_<supf><mode>" - [(match_operand:MVE_2 0 "s_register_operand") - (match_operand:MVE_2 1 "s_register_operand") - (match_operand:SI 2 "s_register_operand") - (match_operand:SI 3 "mve_imm_32") - (unspec:MVE_2 [(const_int 0)] VSHLCQ)] - "TARGET_HAVE_MVE" -{ - rtx ignore_wb = gen_reg_rtx (SImode); - emit_insn(gen_mve_vshlcq_<supf><mode>(operands[0], ignore_wb, operands[1], - operands[2], operands[3])); - DONE; -}) - -(define_expand "mve_vshlcq_carry_<supf><mode>" - [(match_operand:SI 0 "s_register_operand") - (match_operand:MVE_2 1 "s_register_operand") - (match_operand:SI 2 "s_register_operand") - (match_operand:SI 3 "mve_imm_32") - (unspec:MVE_2 [(const_int 0)] VSHLCQ)] - "TARGET_HAVE_MVE" -{ - rtx ignore_vec = gen_reg_rtx (<MODE>mode); - emit_insn(gen_mve_vshlcq_<supf><mode>(ignore_vec, operands[0], operands[1], - operands[2], operands[3])); - DONE; -}) - (define_insn "@mve_vshlcq_<supf><mode>" [(set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0") @@ -6247,38 +6219,6 @@ (define_insn "mve_sqshll_di" ;; ;; [vshlcq_m_u vshlcq_m_s] ;; -(define_expand "mve_vshlcq_m_vec_<supf><mode>" - [(match_operand:MVE_2 0 "s_register_operand") - (match_operand:MVE_2 1 "s_register_operand") - (match_operand:SI 2 "s_register_operand") - (match_operand:SI 3 "mve_imm_32") - (match_operand:<MVE_VPRED> 4 "vpr_register_operand") - (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)] - "TARGET_HAVE_MVE" -{ - rtx ignore_wb = gen_reg_rtx (SImode); - emit_insn (gen_mve_vshlcq_m_<supf><mode> (operands[0], ignore_wb, operands[1], - operands[2], operands[3], - operands[4])); - DONE; -}) - -(define_expand "mve_vshlcq_m_carry_<supf><mode>" - [(match_operand:SI 0 "s_register_operand") - (match_operand:MVE_2 1 "s_register_operand") - (match_operand:SI 2 "s_register_operand") - (match_operand:SI 3 "mve_imm_32") - (match_operand:<MVE_VPRED> 4 "vpr_register_operand") - (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)] - "TARGET_HAVE_MVE" -{ - rtx ignore_vec = gen_reg_rtx (<MODE>mode); - emit_insn (gen_mve_vshlcq_m_<supf><mode> (ignore_vec, operands[0], - operands[1], operands[2], - operands[3], operands[4])); - DONE; -}) - (define_insn "@mve_vshlcq_m_<supf><mode>" [(set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")