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Wed, 04 Sep 2024 06:27:45 -0700 (PDT) Received: from localhost.localdomain ([139.178.84.207]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5dfa0580692sm2308062eaf.46.2024.09.04.06.27.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2024 06:27:44 -0700 (PDT) From: Christophe Lyon To: gcc-patches@gcc.gnu.org, richard.earnshaw@arm.com, ramanara@nvidia.com Cc: Christophe Lyon Subject: [PATCH v2 27/36] arm: [MVE intrinsics] remove useless v[id]wdup expanders Date: Wed, 4 Sep 2024 13:26:41 +0000 Message-Id: <20240904132650.2720446-28-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240904132650.2720446-1-christophe.lyon@linaro.org> References: <20240711214305.3193022-1-christophe.lyon@linaro.org> <20240904132650.2720446-1-christophe.lyon@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Like with vddup/vidup, we use code_for_mve_q_wb_u_insn, so we can drop the expanders and their declarations as builtins, now useless. 2024-08-28 Christophe Lyon gcc/ * config/arm/arm-builtins.cc (arm_quinop_unone_unone_unone_unone_imm_pred_qualifiers): Delete. * config/arm/arm_mve_builtins.def (viwdupq_wb_u, vdwdupq_wb_u) (viwdupq_m_wb_u, vdwdupq_m_wb_u, viwdupq_m_n_u, vdwdupq_m_n_u) (vdwdupq_n_u, viwdupq_n_u): Delete. * config/arm/mve.md (mve_vdwdupq_n_u): Delete. (mve_vdwdupq_wb_u): Delete. (mve_vdwdupq_m_n_u): Delete. (mve_vdwdupq_m_wb_u): Delete. --- gcc/config/arm/arm-builtins.cc | 7 --- gcc/config/arm/arm_mve_builtins.def | 8 --- gcc/config/arm/mve.md | 75 ----------------------------- 3 files changed, 90 deletions(-) diff --git a/gcc/config/arm/arm-builtins.cc b/gcc/config/arm/arm-builtins.cc index c9d50bf8fbb..697b91911dd 100644 --- a/gcc/config/arm/arm-builtins.cc +++ b/gcc/config/arm/arm-builtins.cc @@ -755,13 +755,6 @@ arm_ldru_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_pointer, qualifier_predicate}; #define LDRU_Z_QUALIFIERS (arm_ldru_z_qualifiers) -static enum arm_type_qualifiers -arm_quinop_unone_unone_unone_unone_imm_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] - = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, - qualifier_unsigned, qualifier_immediate, qualifier_predicate }; -#define QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED_QUALIFIERS \ - (arm_quinop_unone_unone_unone_unone_imm_pred_qualifiers) - static enum arm_type_qualifiers arm_ldrgbwbxu_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate}; diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 7e88db4e4c3..f6962cd8cf5 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -799,14 +799,6 @@ VAR1 (STRSU_P, vstrdq_scatter_offset_p_u, v2di) VAR1 (STRSU_P, vstrdq_scatter_shifted_offset_p_u, v2di) VAR1 (STRSU_P, vstrwq_scatter_offset_p_u, v4si) VAR1 (STRSU_P, vstrwq_scatter_shifted_offset_p_u, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, viwdupq_wb_u, v16qi, v4si, v8hi) -VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vdwdupq_wb_u, v16qi, v4si, v8hi) -VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, viwdupq_m_wb_u, v16qi, v8hi, v4si) -VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, vdwdupq_m_wb_u, v16qi, v8hi, v4si) -VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, viwdupq_m_n_u, v16qi, v8hi, v4si) -VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, vdwdupq_m_n_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vdwdupq_n_u, v16qi, v4si, v8hi) -VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, viwdupq_n_u, v16qi, v4si, v8hi) VAR1 (STRSBWBU, vstrwq_scatter_base_wb_u, v4si) VAR1 (STRSBWBU, vstrdq_scatter_base_wb_u, v2di) VAR1 (STRSBWBU_P, vstrwq_scatter_base_wb_p_u, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 72a7e4dc868..0507e117f51 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -5120,41 +5120,6 @@ (define_insn "@mve_q_m_wb_u_insn" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_u_insn")) (set_attr "length""8")]) -;; -;; [vdwdupq_n_u]) -;; -(define_expand "mve_vdwdupq_n_u" - [(match_operand:MVE_2 0 "s_register_operand") - (match_operand:SI 1 "s_register_operand") - (match_operand:DI 2 "s_register_operand") - (match_operand:SI 3 "mve_imm_selective_upto_8")] - "TARGET_HAVE_MVE" -{ - rtx ignore_wb = gen_reg_rtx (SImode); - emit_insn (gen_mve_vdwdupq_wb_u_insn (operands[0], ignore_wb, - operands[1], operands[2], - operands[3])); - DONE; -}) - -;; -;; [vdwdupq_wb_u]) -;; -(define_expand "mve_vdwdupq_wb_u" - [(match_operand:SI 0 "s_register_operand") - (match_operand:SI 1 "s_register_operand") - (match_operand:DI 2 "s_register_operand") - (match_operand:SI 3 "mve_imm_selective_upto_8") - (unspec:MVE_2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] - "TARGET_HAVE_MVE" -{ - rtx ignore_vec = gen_reg_rtx (mode); - emit_insn (gen_mve_vdwdupq_wb_u_insn (ignore_vec, operands[0], - operands[1], operands[2], - operands[3])); - DONE; -}) - ;; ;; [vdwdupq_wb_u_insn, viwdupq_wb_u_insn] ;; @@ -5174,46 +5139,6 @@ (define_insn "@mve_q_wb_u_insn" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_wb_u_insn")) (set_attr "type" "mve_move")]) -;; -;; [vdwdupq_m_n_u]) -;; -(define_expand "mve_vdwdupq_m_n_u" - [(match_operand:MVE_2 0 "s_register_operand") - (match_operand:MVE_2 1 "s_register_operand") - (match_operand:SI 2 "s_register_operand") - (match_operand:DI 3 "s_register_operand") - (match_operand:SI 4 "mve_imm_selective_upto_8") - (match_operand: 5 "vpr_register_operand")] - "TARGET_HAVE_MVE" -{ - rtx ignore_wb = gen_reg_rtx (SImode); - emit_insn (gen_mve_vdwdupq_m_wb_u_insn (operands[0], ignore_wb, - operands[1], operands[2], - operands[3], operands[4], - operands[5])); - DONE; -}) - -;; -;; [vdwdupq_m_wb_u]) -;; -(define_expand "mve_vdwdupq_m_wb_u" - [(match_operand:SI 0 "s_register_operand") - (match_operand:MVE_2 1 "s_register_operand") - (match_operand:SI 2 "s_register_operand") - (match_operand:DI 3 "s_register_operand") - (match_operand:SI 4 "mve_imm_selective_upto_8") - (match_operand: 5 "vpr_register_operand")] - "TARGET_HAVE_MVE" -{ - rtx ignore_vec = gen_reg_rtx (mode); - emit_insn (gen_mve_vdwdupq_m_wb_u_insn (ignore_vec, operands[0], - operands[1], operands[2], - operands[3], operands[4], - operands[5])); - DONE; -}) - ;; ;; [vdwdupq_m_wb_u_insn, viwdupq_m_wb_u_insn] ;;