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[88.127.129.70]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3749ee71650sm11463223f8f.40.2024.09.02.07.07.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Sep 2024 07:07:47 -0700 (PDT) From: Andrew Stubbs To: gcc-patches@gcc.gnu.org Subject: [committed] amdgcn: Remove TARGET_GCN5_PLUS Date: Mon, 2 Sep 2024 14:07:40 +0000 Message-ID: <20240902140740.3760471-3-ams@baylibre.com> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Now that GCN3 support is gone, TARGET_GCN5_PLUS always evaluates to true, so we can make that code unconditional, and remove all the "else" cases. The ISA features TARGET_GLOBAL_ADDRSPACE, TARGET_FLAT_OFFSETS, TARGET_EXPLICIT_CARRY, and TARGET_MULTIPLY_IMMEDIATE, are similarly also redundant and can be made unconditional. The naming of the "gcc_version" attribute has been confusing since the "rdna" attribute was added and this makes it worse, so it has been renamed to "cdna". The add-with-carry assembler mnemonics no longer have two forms, so '%^' can be removed. gcc/ChangeLog: * config/gcn/gcn-opts.h (TARGET_GCN5_PLUS): Delete. (TARGET_GLOBAL_ADDRSPACE): Delete. (TARGET_FLAT_OFFSETS): Delete. (TARGET_EXPLICIT_CARRY): Delete. (TARGET_MULTIPLY_IMMEDIATE): Delete. * config/gcn/gcn-valu.md (*mov): Rename "gcn_version" to "cdna". (*mov_4reg): Likewise. (@mov_sgprbase): Likwise. (gather_insn_1offset): Likewise. (gather_insn_1offset_ds): Likewise. (gather_insn_2offsets): Likewise. (scatter_insn_1offset): Likewise. (scatter_insn_1offset_ds): Likewise. (scatter_insn_2offsets): Likewise. (gather_insn_1offset): Remove TARGET_FLAT_OFFSETS conditionals. (scatter_insn_1offset): Likewise. (scatter_insn_1offset): Likewise. (add3): Use "_co" instead of "%^". (add3_dup): Likewise. (add3_vcc): Likewise. (add3_vcc_dup): Likewise. (addc3): Likewise. (sub3): Likewise. (sub3_vcc): Likewise. (subc3): Likewise. (*plus_carry_dpp_shr_): Likewise. (*plus_carry_in_dpp_shr_): Likewise. * config/gcn/gcn.cc (gcn_flat_address_p): Remove TARGET_FLAT_OFFSETS conditionals. (gcn_addr_space_legitimate_address_p): Likewise. (gcn_addr_space_legitimize_address): Likewise. (gcn_expand_scalar_to_vector_address): Likewise. (print_operand_address): Likewise, and TARGET_GLOBAL_ADDRSPACE also. (print_operand): Remove "%^" operand code. Remove TARGET_GLOBAL_ADDRSPACE assertion. * config/gcn/gcn.h (STACK_ADDR_SPACE): Remove GCN5 conditional. * config/gcn/gcn.md (gcn_version): Rename attribute ... (cdna): ... to this, and remove the gcn3 and gcn5 values. (enabled): Replace old "gcn_version" logic with new "cdna" logic. (*mov_insn): Rename "gcn_version" to "cdna". (*movti_insn): Likewise. (addsi3): Use "_co" instead of "%^". (addsi3_scalar_carry): Likewise. (addsi3_scalar_carry_cst): Likewise. (addcsi3_scalar): Likewise. (addcsi3_scalar_zero): Likewise. (addptrdi3): Likewise. (subsi3): Likewise. (mulsi3_highpart): Remove TARGET_MULTIPLY_IMMEDIATE conditions. (mulsi3_highpart_reg): Remove "gcn_version" attribute. (muldi3): Likewise. (atomic_fetch_): Likewise. (atomic_): Likewise. (sync_compare_and_swap_insn): Likewise. (atomic_load): Likewise. (atomic_store): Likewise. (atomic_exchange): Likewise. (mulsi3_highpart_imm): Remove both TARGET_MULTIPLY_IMMEDIATE and "gcn_version". (mulsidi3): Likewise. (mulsidi3_imm): Likewise. --- gcc/config/gcn/gcn-opts.h | 9 ----- gcc/config/gcn/gcn-valu.md | 72 ++++++++++++++++--------------------- gcc/config/gcn/gcn.cc | 36 +++---------------- gcc/config/gcn/gcn.h | 3 +- gcc/config/gcn/gcn.md | 74 +++++++++++++------------------------- 5 files changed, 59 insertions(+), 135 deletions(-) diff --git a/gcc/config/gcn/gcn-opts.h b/gcc/config/gcn/gcn-opts.h index 6f5969d7bc8..76f50ab9364 100644 --- a/gcc/config/gcn/gcn-opts.h +++ b/gcc/config/gcn/gcn-opts.h @@ -52,7 +52,6 @@ extern enum gcn_isa { } gcn_isa; #define TARGET_GCN5 (gcn_isa == ISA_GCN5) -#define TARGET_GCN5_PLUS (gcn_isa >= ISA_GCN5) #define TARGET_CDNA1 (gcn_isa == ISA_CDNA1) #define TARGET_CDNA1_PLUS (gcn_isa >= ISA_CDNA1) #define TARGET_CDNA2 (gcn_isa == ISA_CDNA2) @@ -74,16 +73,12 @@ enum hsaco_attr_type HSACO_ATTR_DEFAULT }; -/* There are global address instructions. */ -#define TARGET_GLOBAL_ADDRSPACE TARGET_GCN5_PLUS /* Device has an AVGPR register file. */ #define TARGET_AVGPRS TARGET_CDNA1_PLUS /* There are load/store instructions for AVGPRS. */ #define TARGET_AVGPR_MEMOPS TARGET_CDNA2_PLUS /* AVGPRS may have their own register file, or be combined with VGPRS. */ #define TARGET_AVGPR_COMBINED TARGET_CDNA2_PLUS -/* flat_load/store allows offsets. */ -#define TARGET_FLAT_OFFSETS TARGET_GCN5_PLUS /* global_load/store has reduced offset. */ #define TARGET_11BIT_GLOBAL_OFFSET TARGET_RDNA2_PLUS /* The work item details are all encoded into v0. */ @@ -106,10 +101,6 @@ enum hsaco_attr_type : 4) /* This mostly affects the metadata. */ #define TARGET_ARCHITECTED_FLAT_SCRATCH TARGET_RDNA3 -/* Assembler uses s_add_co not just s_add. */ -#define TARGET_EXPLICIT_CARRY TARGET_GCN5_PLUS -/* mulsi3 permits immediate. */ -#define TARGET_MULTIPLY_IMMEDIATE TARGET_GCN5_PLUS /* Device has Sub-DWord Addressing instrucions. */ #define TARGET_SDWA (!TARGET_RDNA3) /* Different devices uses different cache control instructions. */ diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index 54f4b14d4f2..cb2f4a78035 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -452,7 +452,7 @@ (define_insn "*mov" [(set (match_operand:V_1REG 0 "nonimmediate_operand") (match_operand:V_1REG 1 "general_operand"))] "" - {@ [cons: =0, 1; attrs: type, length, gcn_version] + {@ [cons: =0, 1; attrs: type, length, cdna] [v ,vA;vop1 ,4,* ] v_mov_b32\t%0, %1 [v ,B ;vop1 ,8,* ] ^ [v ,a ;vop3p_mai,8,* ] v_accvgpr_read_b32\t%0, %1 @@ -519,7 +519,7 @@ (define_insn "*mov" return \"v_accvgpr_mov_b32\t%H0, %H1\;v_accvgpr_mov_b32\t%L0, %L1\";" [(set_attr "type" "vmult,vmult,vmult,vmult") (set_attr "length" "16,16,16,8") - (set_attr "gcn_version" "*,*,*,cdna2")]) + (set_attr "cdna" "*,*,*,cdna2")]) (define_insn "mov_exec" [(set (match_operand:V_2REG 0 "nonimmediate_operand" "= v, v, v, v, m") @@ -565,7 +565,7 @@ (define_insn "*mov_4reg" [(set (match_operand:V_4REG 0 "nonimmediate_operand") (match_operand:V_4REG 1 "general_operand"))] "" - {@ [cons: =0, 1; attrs: type, length, gcn_version] + {@ [cons: =0, 1; attrs: type, length, cdna] [v ,vDB;vmult,16,* ] v_mov_b32\t%L0, %L1\; v_mov_b32\t%H0, %H1\; v_mov_b32\t%J0, %J1\; v_mov_b32\t%K0, %K1 [v ,a ;vmult,32,* ] v_accvgpr_read_b32\t%L0, %L1\; v_accvgpr_read_b32\t%H0, %H1\; v_accvgpr_read_b32\t%J0, %J1\; v_accvgpr_read_b32\t%K0, %K1 [$a,v ;vmult,32,* ] v_accvgpr_write_b32\t%L0, %L1\;v_accvgpr_write_b32\t%H0, %H1\;v_accvgpr_write_b32\t%J0, %J1\;v_accvgpr_write_b32\t%K0, %K1 @@ -662,7 +662,7 @@ (define_insn "@mov_sgprbase" UNSPEC_SGPRBASE)) (clobber (match_operand: 2 "register_operand"))] "lra_in_progress || reload_completed" - {@ [cons: =0, 1, =2; attrs: type, length, gcn_version] + {@ [cons: =0, 1, =2; attrs: type, length, cdna] [v,vA,&v;vop1,4 ,* ] v_mov_b32\t%0, %1 [v,vB,&v;vop1,8 ,* ] ^ [v,m ,&v;* ,12,* ] # @@ -689,7 +689,7 @@ (define_insn "@mov_sgprbase" #" [(set_attr "type" "vmult,*,*,*,*") (set_attr "length" "8,12,12,12,12") - (set_attr "gcn_version" "*,*,*,cdna2,cdna2")]) + (set_attr "cdna" "*,*,*,cdna2,cdna2")]) (define_insn "@mov_sgprbase" [(set (match_operand:V_4REG 0 "nonimmediate_operand") @@ -1165,13 +1165,7 @@ (define_insn "gather_insn_1offset" static char buf[200]; if (AS_FLAT_P (as)) - { - if (TARGET_FLAT_OFFSETS) - sprintf (buf, "flat_load%%o0\t%%0, %%1 offset:%%2%s\;s_waitcnt\t0", - glc); - else - sprintf (buf, "flat_load%%o0\t%%0, %%1%s\;s_waitcnt\t0", glc); - } + sprintf (buf, "flat_load%%o0\t%%0, %%1 offset:%%2%s\;s_waitcnt\t0", glc); else if (AS_GLOBAL_P (as)) sprintf (buf, "global_load%%o0\t%%0, %%1, off offset:%%2%s\;" "s_waitcnt\tvmcnt(0)", glc); @@ -1182,7 +1176,7 @@ (define_insn "gather_insn_1offset" } [(set_attr "type" "flat") (set_attr "length" "12") - (set_attr "gcn_version" "*,cdna2,*,cdna2") + (set_attr "cdna" "*,cdna2,*,cdna2") (set_attr "xnack" "off,off,on,on")]) (define_insn "gather_insn_1offset_ds" @@ -1206,7 +1200,7 @@ (define_insn "gather_insn_1offset_ds" } [(set_attr "type" "ds") (set_attr "length" "12") - (set_attr "gcn_version" "*,cdna2")]) + (set_attr "cdna" "*,cdna2")]) (define_insn "gather_insn_2offsets" [(set (match_operand:V_MOV 0 "register_operand" "=v,a,&v,&a") @@ -1240,7 +1234,7 @@ (define_insn "gather_insn_2offsets" } [(set_attr "type" "flat") (set_attr "length" "12") - (set_attr "gcn_version" "*,cdna2,*,cdna2") + (set_attr "cdna" "*,cdna2,*,cdna2") (set_attr "xnack" "off,off,on,on")]) (define_expand "scatter_store" @@ -1289,8 +1283,7 @@ (define_insn "scatter_insn_1offset" UNSPEC_SCATTER))] "(AS_FLAT_P (INTVAL (operands[3])) && (INTVAL(operands[1]) == 0 - || (TARGET_FLAT_OFFSETS - && (unsigned HOST_WIDE_INT)INTVAL(operands[1]) < 0x1000))) + || ((unsigned HOST_WIDE_INT)INTVAL(operands[1]) < 0x1000))) || (AS_GLOBAL_P (INTVAL (operands[3])) && (((unsigned HOST_WIDE_INT)INTVAL(operands[1]) + 0x1000) < 0x2000))" { @@ -1299,12 +1292,7 @@ (define_insn "scatter_insn_1offset" static char buf[200]; if (AS_FLAT_P (as)) - { - if (TARGET_FLAT_OFFSETS) sprintf (buf, "flat_store%%s2\t%%0, %%2 offset:%%1%s", glc); - else - sprintf (buf, "flat_store%%s2\t%%0, %%2%s", glc); - } else if (AS_GLOBAL_P (as)) sprintf (buf, "global_store%%s2\t%%0, %%2, off offset:%%1%s", glc); else @@ -1314,7 +1302,7 @@ (define_insn "scatter_insn_1offset" } [(set_attr "type" "flat") (set_attr "length" "12") - (set_attr "gcn_version" "*,cdna2")]) + (set_attr "cdna" "*,cdna2")]) (define_insn "scatter_insn_1offset_ds" [(set (mem:BLK (scratch)) @@ -1337,7 +1325,7 @@ (define_insn "scatter_insn_1offset_ds" } [(set_attr "type" "ds") (set_attr "length" "12") - (set_attr "gcn_version" "*,cdna2")]) + (set_attr "cdna" "*,cdna2")]) (define_insn "scatter_insn_2offsets" [(set (mem:BLK (scratch)) @@ -1369,7 +1357,7 @@ (define_insn "scatter_insn_2offsets" } [(set_attr "type" "flat") (set_attr "length" "12") - (set_attr "gcn_version" "*,cdna2")]) + (set_attr "cdna" "*,cdna2")]) ;; }}} ;; {{{ Permutations @@ -1475,7 +1463,7 @@ (define_insn "add3" (clobber (reg:DI VCC_REG))] "" {@ [cons: =0, %1, 2; attrs: type, length] - [v,v,vSvA;vop2,4] v_add%^_u32\t%0, vcc, %2, %1 + [v,v,vSvA;vop2,4] v_add_co_u32\t%0, vcc, %2, %1 [v,v,vSvB;vop2,8] ^ }) @@ -1488,7 +1476,7 @@ (define_insn "add3_dup" (clobber (reg:DI VCC_REG))] "" {@ [cons: =0, 1, 2; attrs: type, length] - [v,v,SvA;vop2,4] v_add%^_u32\t%0, vcc, %2, %1 + [v,v,SvA;vop2,4] v_add_co_u32\t%0, vcc, %2, %1 [v,v,SvB;vop2,8] ^ }) @@ -1502,7 +1490,7 @@ (define_insn "add3_vcc" (match_dup 1)))] "" {@ [cons: =0, %1, 2, =3; attrs: type, length] - [v,v,vSvA,cV;vop2 ,4] v_add%^_u32\t%0, %3, %2, %1 + [v,v,vSvA,cV;vop2 ,4] v_add_co_u32\t%0, %3, %2, %1 [v,v,vSvB,cV;vop2 ,8] ^ [v,v,vSvA,Sg;vop3b,8] ^ }) @@ -1522,7 +1510,7 @@ (define_insn "add3_vcc_dup" (vec_duplicate:V_SI (match_dup 2))))] "" {@ [cons: =0, 1, 2, =3; attrs: type, length] - [v,SvA,v,cV;vop2 ,4] v_add%^_u32\t%0, %3, %1, %2 + [v,SvA,v,cV;vop2 ,4] v_add_co_u32\t%0, %3, %1, %2 [v,SvB,v,cV;vop2 ,8] ^ [v,SvA,v,Sg;vop3b,8] ^ }) @@ -1559,7 +1547,7 @@ (define_insn "addc3" (match_dup 1)) (match_dup 1))))] "" - "{v_addc%^_u32|v_add_co_ci_u32}\t%0, %4, %2, %1, %3" + "{v_addc_co_u32|v_add_co_ci_u32}\t%0, %4, %2, %1, %3" [(set_attr "type" "vop2,vop3b") (set_attr "length" "4,8")]) @@ -1571,8 +1559,8 @@ (define_insn "sub3" (clobber (reg:DI VCC_REG))] "" "@ - v_sub%^_u32\t%0, vcc, %1, %2 - v_subrev%^_u32\t%0, vcc, %2, %1" + v_sub_co_u32\t%0, vcc, %1, %2 + v_subrev_co_u32\t%0, vcc, %2, %1" [(set_attr "type" "vop2") (set_attr "length" "8,8")]) @@ -1586,10 +1574,10 @@ (define_insn "sub3_vcc" (match_dup 1)))] "" "@ - v_sub%^_u32\t%0, %3, %1, %2 - v_sub%^_u32\t%0, %3, %1, %2 - v_subrev%^_u32\t%0, %3, %2, %1 - v_subrev%^_u32\t%0, %3, %2, %1" + v_sub_co_u32\t%0, %3, %1, %2 + v_sub_co_u32\t%0, %3, %1, %2 + v_subrev_co_u32\t%0, %3, %2, %1 + v_subrev_co_u32\t%0, %3, %2, %1" [(set_attr "type" "vop2,vop3b,vop2,vop3b") (set_attr "length" "8")]) @@ -1624,10 +1612,10 @@ (define_insn "subc3" (match_dup 1))))] "" "@ - {v_subb%^_u32|v_sub_co_ci_u32}\t%0, %4, %1, %2, %3 - {v_subb%^_u32|v_sub_co_ci_u32}\t%0, %4, %1, %2, %3 - {v_subbrev%^_u32|v_subrev_co_ci_u32}\t%0, %4, %2, %1, %3 - {v_subbrev%^_u32|v_subrev_co_ci_u32}\t%0, %4, %2, %1, %3" + {v_subb_co_u32|v_sub_co_ci_u32}\t%0, %4, %1, %2, %3 + {v_subb_co_u32|v_sub_co_ci_u32}\t%0, %4, %1, %2, %3 + {v_subbrev_co_u32|v_subrev_co_ci_u32}\t%0, %4, %2, %1, %3 + {v_subbrev_co_u32|v_subrev_co_ci_u32}\t%0, %4, %2, %1, %3" [(set_attr "type" "vop2,vop3b,vop2,vop3b") (set_attr "length" "4,8,4,8")]) @@ -4343,7 +4331,7 @@ (define_insn "*plus_carry_dpp_shr_" (clobber (reg:DI VCC_REG))] "TARGET_DPP_FULL" { - return gcn_expand_dpp_shr_insn (mode, "v_add%^_u32", + return gcn_expand_dpp_shr_insn (mode, "v_add_co_u32", UNSPEC_PLUS_CARRY_DPP_SHR, INTVAL (operands[3])); } @@ -4361,7 +4349,7 @@ (define_insn "*plus_carry_in_dpp_shr_" (clobber (reg:DI VCC_REG))] "TARGET_DPP_FULL" { - return gcn_expand_dpp_shr_insn (mode, "v_addc%^_u32", + return gcn_expand_dpp_shr_insn (mode, "v_addc_co_u32", UNSPEC_PLUS_CARRY_IN_DPP_SHR, INTVAL (operands[3])); } diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc index fd2b8608574..db48a6776b1 100644 --- a/gcc/config/gcn/gcn.cc +++ b/gcc/config/gcn/gcn.cc @@ -1528,8 +1528,7 @@ gcn_flat_address_p (rtx x, machine_mode mode) if (!vec_mode && gcn_vec_address_register_p (x, DImode, false)) return true; - if (TARGET_FLAT_OFFSETS - && GET_CODE (x) == PLUS + if (GET_CODE (x) == PLUS && gcn_vec_address_register_p (XEXP (x, 0), DImode, false) && CONST_INT_P (XEXP (x, 1))) return true; @@ -1640,10 +1639,6 @@ static bool gcn_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict, addr_space_t as, code_helper = ERROR_MARK) { - /* All vector instructions need to work on addresses in registers. */ - if (!TARGET_FLAT_OFFSETS && (vgpr_vector_mode_p (mode) && !REG_P (x))) - return false; - if (AS_SCALAR_FLAT_P (as)) { if (mode == QImode || mode == HImode) @@ -1689,15 +1684,13 @@ gcn_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict, return gcn_address_register_p (x, SImode, strict); else if (AS_FLAT_P (as) || AS_FLAT_SCRATCH_P (as)) { - if (!TARGET_FLAT_OFFSETS || GET_CODE (x) == REG) + if (GET_CODE (x) == REG) return ((GET_MODE_CLASS (mode) == MODE_VECTOR_INT || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) ? gcn_address_register_p (x, DImode, strict) : gcn_vec_address_register_p (x, DImode, strict)); else { - gcc_assert (TARGET_FLAT_OFFSETS); - if (GET_CODE (x) == PLUS) { rtx x1 = XEXP (x, 1); @@ -1721,8 +1714,6 @@ gcn_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict, } else if (AS_GLOBAL_P (as)) { - gcc_assert (TARGET_FLAT_OFFSETS); - if (GET_CODE (x) == REG) return (gcn_address_register_p (x, DImode, strict) || (!VECTOR_MODE_P (mode) @@ -2199,7 +2190,7 @@ gcn_addr_space_legitimize_address (rtx x, rtx old, machine_mode mode, case ADDR_SPACE_FLAT: case ADDR_SPACE_FLAT_SCRATCH: case ADDR_SPACE_GLOBAL: - return !TARGET_FLAT_OFFSETS ? force_reg (DImode, x) : x; + return x; case ADDR_SPACE_LDS: case ADDR_SPACE_GDS: /* FIXME: LDS support offsets, handle them!. */ @@ -2237,13 +2228,6 @@ gcn_expand_scalar_to_vector_address (machine_mode mode, rtx exec, rtx mem, rtx mem_base = XEXP (mem, 0); rtx mem_index = NULL_RTX; - if (!TARGET_FLAT_OFFSETS) - { - /* gcn_addr_space_legitimize_address should have put the address in a - register. If not, it is too late to do anything about it. */ - gcc_assert (REG_P (mem_base)); - } - if (GET_CODE (mem_base) == PLUS) { mem_index = XEXP (mem_base, 1); @@ -7047,15 +7031,10 @@ print_operand_address (FILE *file, rtx mem) if (GET_CODE (addr) == REG) print_reg (file, addr); else - { - gcc_assert (TARGET_FLAT_OFFSETS); - print_reg (file, XEXP (addr, 0)); - } + print_reg (file, XEXP (addr, 0)); } else if (AS_GLOBAL_P (as)) { - gcc_assert (TARGET_GLOBAL_ADDRSPACE); - rtx base = addr; rtx vgpr_offset = NULL_RTX; @@ -7167,7 +7146,6 @@ print_operand_address (FILE *file, rtx mem) E - print conditional code for v_cmp (eq_u64/ne_u64...) A - print address in formatting suitable for given address space. O - print offset:n for data share operations. - ^ - print "_co" suffix for GCN5 mnemonics g - print "glc", if appropriate for given MEM L - print low-part of a multi-reg value H - print second part of a multi-reg value (high-part of 2-reg value) @@ -7416,8 +7394,6 @@ print_operand (FILE *file, rtx x, int code) rtx x0 = XEXP (x, 0); if (AS_GLOBAL_P (MEM_ADDR_SPACE (x))) { - gcc_assert (TARGET_GLOBAL_ADDRSPACE); - fprintf (file, ", "); rtx base = x0; @@ -7786,10 +7762,6 @@ print_operand (FILE *file, rtx x, int code) else output_addr_const (file, x); return; - case '^': - if (TARGET_EXPLICIT_CARRY) - fputs ("_co", file); - return; case 'g': gcc_assert (xcode == MEM); if (MEM_VOLATILE_P (x)) diff --git a/gcc/config/gcn/gcn.h b/gcc/config/gcn/gcn.h index 70bece7f947..1a4631dd39f 100644 --- a/gcc/config/gcn/gcn.h +++ b/gcc/config/gcn/gcn.h @@ -574,8 +574,7 @@ enum gcn_address_spaces c_register_addr_space ("__global", ADDR_SPACE_GLOBAL); \ } while (0); -#define STACK_ADDR_SPACE \ - (TARGET_GCN5_PLUS ? ADDR_SPACE_GLOBAL : ADDR_SPACE_FLAT) +#define STACK_ADDR_SPACE ADDR_SPACE_GLOBAL #define DEFAULT_ADDR_SPACE \ ((cfun && cfun->machine && !cfun->machine->use_flat_addressing) \ ? ADDR_SPACE_GLOBAL : ADDR_SPACE_FLAT) diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md index f223ec99e7c..8b6ae85e534 100644 --- a/gcc/config/gcn/gcn.md +++ b/gcc/config/gcn/gcn.md @@ -286,7 +286,7 @@ (define_attr "length" "" ; Disable alternatives that only apply to specific ISA variants. -(define_attr "gcn_version" "gcn3,gcn5,cdna2" (const_string "gcn3")) +(define_attr "cdna" "any,cdna2" (const_string "any")) (define_attr "rdna" "any,no,yes" (const_string "any")) (define_attr "xnack" "na,off,on" (const_string "na")) @@ -298,10 +298,7 @@ (define_attr "enabled" "" (and (eq_attr "rdna" "yes") (eq (symbol_ref "TARGET_RDNA2_PLUS") (const_int 0))) (const_int 0) - (and (eq_attr "gcn_version" "gcn5") - (eq (symbol_ref "TARGET_GCN5_PLUS") (const_int 0))) - (const_int 0) - (and (eq_attr "gcn_version" "cdna2") + (and (eq_attr "cdna" "cdna2") (eq (symbol_ref "TARGET_CDNA2_PLUS") (const_int 0))) (const_int 0) (and (eq_attr "xnack" "off") @@ -568,7 +565,7 @@ (define_insn "*mov_insn" [(set (match_operand:SISF 0 "nonimmediate_operand") (match_operand:SISF 1 "gcn_load_operand"))] "" - {@ [cons: =0, 1; attrs: type, exec, length, gcn_version, xnack] + {@ [cons: =0, 1; attrs: type, exec, length, cdna, xnack] [SD ,SSA ;sop1 ,* ,4 ,* ,* ] s_mov_b32\t%0, %1 [SD ,J ;sopk ,* ,4 ,* ,* ] s_movk_i32\t%0, %1 [SD ,B ;sop1 ,* ,8 ,* ,* ] s_mov_b32\t%0, %1 @@ -609,7 +606,7 @@ (define_insn "*mov_insn" [(set (match_operand:QIHI 0 "nonimmediate_operand") (match_operand:QIHI 1 "gcn_load_operand"))] "gcn_valid_move_p (mode, operands[0], operands[1])" - {@ [cons: =0, 1; attrs: type, exec, length, gcn_version, xnack] + {@ [cons: =0, 1; attrs: type, exec, length, cdna, xnack] [SD ,SSA ;sop1 ,* ,4 ,* ,* ] s_mov_b32\t%0, %1 [SD ,J ;sopk ,* ,4 ,* ,* ] s_movk_i32\t%0, %1 [SD ,B ;sop1 ,* ,8 ,* ,* ] s_mov_b32\t%0, %1 @@ -642,7 +639,7 @@ (define_insn_and_split "*mov_insn" [(set (match_operand:DIDF 0 "nonimmediate_operand") (match_operand:DIDF 1 "general_operand"))] "GET_CODE(operands[1]) != SYMBOL_REF" - {@ [cons: =0, 1; attrs: type, length, gcn_version, xnack] + {@ [cons: =0, 1; attrs: type, length, cdna, xnack] [SD ,SSA ;sop1 ,4 ,* ,* ] s_mov_b64\t%0, %1 [SD ,C ;sop1 ,8 ,* ,* ] ^ [SD ,DB ;mult ,* ,* ,* ] # @@ -707,7 +704,7 @@ (define_insn_and_split "*movti_insn" [(set (match_operand:TI 0 "nonimmediate_operand") (match_operand:TI 1 "general_operand" ))] "" - {@ [cons: =0, 1; attrs: type, delayeduse, length, gcn_version, xnack] + {@ [cons: =0, 1; attrs: type, delayeduse, length, cdna, xnack] [SD ,SSB;mult ,* ,* ,* ,* ] # [RS ,Sm ;smem ,* ,12,* ,* ] s_store_dwordx4\t%1, %A0 [Sm ,RS ;smem ,yes,12,* ,off] s_load_dwordx4\t%0, %A1\;s_waitcnt\tlgkmcnt(0) @@ -1137,7 +1134,7 @@ (define_insn "addsi3" s_add_i32\t%0, %1, %2 s_addk_i32\t%0, %2 s_add_i32\t%0, %1, %2 - v_add%^_u32\t%0, vcc, %2, %1" + v_add_co_u32\t%0, vcc, %2, %1" [(set_attr "type" "sop2,sopk,sop2,vop2") (set_attr "length" "4,4,8,8")]) @@ -1217,7 +1214,7 @@ (define_insn "addsi3_scalar_carry" "" "@ s_add_u32\t%0, %1, %2 - v_add%^_u32\t%0, vcc, %2, %1" + v_add_co_u32\t%0, vcc, %2, %1" [(set_attr "type" "sop2,vop2") (set_attr "length" "8,8")]) @@ -1232,7 +1229,7 @@ (define_insn "addsi3_scalar_carry_cst" "INTVAL (operands[2]) == -INTVAL (operands[3])" "@ s_add_u32\t%0, %1, %2 - v_add%^_u32\t%0, vcc, %2, %1" + v_add_co_u32\t%0, vcc, %2, %1" [(set_attr "type" "sop2,vop2") (set_attr "length" "4")]) @@ -1254,7 +1251,7 @@ (define_insn "addcsi3_scalar" "" "@ s_addc_u32\t%0, %1, %2 - {v_addc%^_u32|v_add_co_ci_u32}\t%0, vcc, %2, %1, vcc" + {v_addc_co_u32|v_add_co_ci_u32}\t%0, vcc, %2, %1, vcc" [(set_attr "type" "sop2,vop2") (set_attr "length" "8,4")]) @@ -1270,7 +1267,7 @@ (define_insn "addcsi3_scalar_zero" "" "@ s_addc_u32\t%0, %1, 0 - {v_addc%^_u32|v_add_co_ci_u32}\t%0, vcc, 0, %1, vcc" + {v_addc_co_u32|v_add_co_ci_u32}\t%0, vcc, 0, %1, vcc" [(set_attr "type" "sop2,vop2") (set_attr "length" "4")]) @@ -1299,8 +1296,8 @@ (define_insn "addptrdi3" rtx new_operands[4] = { operands[0], operands[1], operands[2], gen_rtx_REG (DImode, CC_SAVE_REG) }; - output_asm_insn ("v_add%^_u32\t%L0, %3, %L2, %L1", new_operands); - output_asm_insn ("{v_addc%^_u32|v_add_co_ci_u32}\t%H0, %3, %H2, %H1, %3", + output_asm_insn ("v_add_co_u32\t%L0, %3, %L2, %L1", new_operands); + output_asm_insn ("{v_addc_co_u32|v_add_co_ci_u32}\t%H0, %3, %H2, %H1, %3", new_operands); } else @@ -1332,8 +1329,8 @@ (define_insn "subsi3" "@ s_sub_i32\t%0, %1, %2 s_sub_i32\t%0, %1, %2 - v_subrev%^_u32\t%0, vcc, %2, %1 - v_sub%^_u32\t%0, vcc, %1, %2" + v_subrev_co_u32\t%0, vcc, %2, %1 + v_sub_co_u32\t%0, vcc, %1, %2" [(set_attr "type" "sop2,sop2,vop2,vop2") (set_attr "length" "4,8,8,8")]) @@ -1462,11 +1459,6 @@ (define_expand "mulsi3_highpart" (const_int 32))))] "" { - if (can_create_pseudo_p () - && !TARGET_MULTIPLY_IMMEDIATE - && !gcn_inline_immediate_operand (operands[2], SImode)) - operands[2] = force_reg (SImode, operands[2]); - if (REG_P (operands[2])) emit_insn (gen_mulsi3_highpart_reg (operands[0], operands[1], operands[2])); @@ -1492,8 +1484,7 @@ (define_insn "mulsi3_highpart_reg" s_mul_hi0\t%0, %1, %2 v_mul_hi0\t%0, %2, %1" [(set_attr "type" "sop2,vop3a") - (set_attr "length" "4,8") - (set_attr "gcn_version" "gcn5,*")]) + (set_attr "length" "4,8")]) (define_insn "mulsi3_highpart_imm" [(set (match_operand:SI 0 "register_operand" "=Sg,Sg,v") @@ -1504,15 +1495,13 @@ (define_insn "mulsi3_highpart_imm" (match_operand:SI 1 "register_operand" "Sg,Sg,v")) (match_operand:DI 2 "gcn_32bit_immediate_operand" "A, B,A")) (const_int 32))))] - "TARGET_MULTIPLY_IMMEDIATE - || gcn_inline_immediate_operand (operands[2], SImode)" + "" "@ s_mul_hi0\t%0, %1, %2 s_mul_hi0\t%0, %1, %2 v_mul_hi0\t%0, %2, %1" [(set_attr "type" "sop2,sop2,vop3a") - (set_attr "length" "4,8,8") - (set_attr "gcn_version" "gcn5,gcn5,*")]) + (set_attr "length" "4,8,8")]) (define_expand "mulsidi3" [(set (match_operand:DI 0 "register_operand" "") @@ -1522,11 +1511,6 @@ (define_expand "mulsidi3" (match_operand:SI 2 "nonmemory_operand" ""))))] "" { - if (can_create_pseudo_p () - && !TARGET_MULTIPLY_IMMEDIATE - && !gcn_inline_immediate_operand (operands[2], SImode)) - operands[2] = force_reg (SImode, operands[2]); - if (REG_P (operands[2])) emit_insn (gen_mulsidi3_reg (operands[0], operands[1], operands[2])); else @@ -1551,8 +1535,7 @@ (define_insn_and_split "mulsidi3_reg" emit_insn (gen_mulsi3 (dstlo, operands[1], operands[2])); emit_insn (gen_mulsi3_highpart (dsthi, operands[1], operands[2])); DONE; - } - [(set_attr "gcn_version" "gcn5,*")]) + }) (define_insn_and_split "mulsidi3_imm" [(set (match_operand:DI 0 "register_operand" "=&Sg,&Sg,&v") @@ -1560,8 +1543,7 @@ (define_insn_and_split "mulsidi3_imm" (match_operand:SI 1 "register_operand" "Sg, Sg, v")) (match_operand:DI 2 "gcn_32bit_immediate_operand" "A, B, A")))] - "TARGET_MULTIPLY_IMMEDIATE - || gcn_inline_immediate_operand (operands[2], SImode)" + "" "#" "&& reload_completed" [(const_int 0)] @@ -1571,8 +1553,7 @@ (define_insn_and_split "mulsidi3_imm" emit_insn (gen_mulsi3 (dstlo, operands[1], operands[2])); emit_insn (gen_mulsi3_highpart (dsthi, operands[1], operands[2])); DONE; - } - [(set_attr "gcn_version" "gcn5,gcn5,*")]) + }) (define_insn_and_split "muldi3" [(set (match_operand:DI 0 "register_operand" "=&Sg,&Sg, &v,&v") @@ -1606,8 +1587,7 @@ (define_insn_and_split "muldi3" add = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3, add, clob1, clob2)); emit_insn (add); DONE; - } - [(set_attr "gcn_version" "gcn5,gcn5,*,*")]) + }) (define_insn "mulhisi3" [(set (match_operand:SI 0 "register_operand" "=v") @@ -1994,8 +1974,7 @@ (define_insn "atomic_fetch_" flat_atomic_\t%0, %1, %2 glc\;s_waitcnt\t0 global_atomic_\t%0, %A1, %2%O1 glc\;s_waitcnt\tvmcnt(0)" [(set_attr "type" "smem,flat,flat") - (set_attr "length" "12") - (set_attr "gcn_version" "gcn5,*,gcn5")]) + (set_attr "length" "12")]) ; FIXME: These patterns are disabled because the instructions don't ; seem to work as advertised. Specifically, OMP "team distribute" @@ -2016,8 +1995,7 @@ (define_insn "atomic_" flat_atomic_\t%0, %1\;s_waitcnt\t0 global_atomic_\t%A0, %1%O0\;s_waitcnt\tvmcnt(0)" [(set_attr "type" "smem,flat,flat") - (set_attr "length" "12") - (set_attr "gcn_version" "gcn5,*,gcn5")]) + (set_attr "length" "12")]) (define_mode_attr x2 [(SI "DI") (DI "TI")]) (define_mode_attr size [(SI "4") (DI "8")]) @@ -2064,7 +2042,6 @@ (define_insn "sync_compare_and_swap_insn" global_atomic_cmpswap\t%0, %A1, %2%O1 glc\;s_waitcnt\tvmcnt(0)" [(set_attr "type" "smem,flat,flat") (set_attr "length" "12") - (set_attr "gcn_version" "gcn5,*,gcn5") (set_attr "delayeduse" "*,yes,yes")]) (define_insn "sync_compare_and_swap_lds_insn" @@ -2174,7 +2151,6 @@ (define_insn "atomic_load" } [(set_attr "type" "smem,flat,flat") (set_attr "length" "28") - (set_attr "gcn_version" "gcn5,*,gcn5") (set_attr "rdna" "no,*,*")]) (define_insn "atomic_store" @@ -2249,7 +2225,6 @@ (define_insn "atomic_store" } [(set_attr "type" "smem,flat,flat") (set_attr "length" "28") - (set_attr "gcn_version" "gcn5,*,gcn5") (set_attr "rdna" "no,*,*")]) (define_insn "atomic_exchange" @@ -2362,7 +2337,6 @@ (define_insn "atomic_exchange" } [(set_attr "type" "smem,flat,flat") (set_attr "length" "28") - (set_attr "gcn_version" "gcn5,*,gcn5") (set_attr "rdna" "no,*,*")]) ;; }}}