From patchwork Mon Sep 2 11:27:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1979609 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=e4BZ1OzN; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Wy63921mkz1yXY for ; Mon, 2 Sep 2024 21:29:05 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4251F384DD04 for ; Mon, 2 Sep 2024 11:29:02 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by sourceware.org (Postfix) with ESMTPS id 78279385DDD3 for ; Mon, 2 Sep 2024 11:28:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 78279385DDD3 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 78279385DDD3 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1725276522; cv=none; b=luVBhAqWnF+wtFeo2tgEuEwxRRU+BxTm44JwknU/v3h2HI4N/W6W9B7BYzhn26R0t1Wha1dyju6dSS5Oqhi1cSwXJ6qZrNh+sw2rpZUYbFeP3sw00mO+FkiXleMY9mjcnfAB5a3YTIEevKkckr16PeBo9MGLOBTimOBLMCoD0H0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1725276522; c=relaxed/simple; bh=5TXHBifJJVeX3eO6z5gAcRyc+wuvWWshcme79JDmjco=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=wRRYG8hy+pkBVmrLlWJ1kT/lIHcjqf+/RBq0f6qA0rXhS34KmyWPpntQBv5BuAHSOe9WCyA1eAuWjDbx763VAIcR0A8jTFbQPYu5BOpHcuI9QJNt7+Gb87/QiPoRjys8sH5sZ1w2gy6jIQswcML0ZJVuMWZyOQwIRayS83Qbfxg= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1725276520; x=1756812520; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=5TXHBifJJVeX3eO6z5gAcRyc+wuvWWshcme79JDmjco=; b=e4BZ1OzNbcqrvrUEHzZGS6VpiKEqK+EgKb2mCWNLDMznSxGZp8rf7MdF f6YM3F2q9p6yoLUjYPshYbuSmhOrPX/N2rGTyZ+3FWs9Cjm05NECvK1bT 9moQwSjXtkrWkJTyBLSeruMW1fBNLMMwIRDq8VnnRqFAytTLWqTykNySb 83ezS2sxB2dFN1GuHM51xSIMt13N8gpmvhyEF5OZCJWSgAxye6APN0bMA tu+2Z/PdVvho8RS/l0HRVDkzdGg1j1rNBXIpUBbwkLyFYCWbgDHm5hQUM N9UptCx7BeuoQfOHRxh7yb5JpHPDSKJWKYHsy6v9/Csg701GHFER9GaEs g==; X-CSE-ConnectionGUID: 0fvaH5GgRq27MKgZkHoppQ== X-CSE-MsgGUID: tywJ/niWSCCdF3m4q0KdVg== X-IronPort-AV: E=McAfee;i="6700,10204,11182"; a="24011424" X-IronPort-AV: E=Sophos;i="6.10,195,1719903600"; d="scan'208";a="24011424" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Sep 2024 04:28:38 -0700 X-CSE-ConnectionGUID: 2WNltj7CRZ+nfvKPwrn4eg== X-CSE-MsgGUID: f0JTQaqBSJOnaRZIDUfKew== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,195,1719903600"; d="scan'208";a="65298629" Received: from panli.sh.intel.com ([10.239.154.73]) by orviesa008.jf.intel.com with ESMTP; 02 Sep 2024 04:28:36 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1] RISC-V: Allow IMM operand for unsigned scalar .SAT_ADD Date: Mon, 2 Sep 2024 19:27:53 +0800 Message-ID: <20240902112753.4115540-1-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_BLACK, URIBL_SBL_A autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch would like to allow the IMM operand of the unsigned scalar .SAT_ADD. Like the operand 0, the operand 1 of .SAT_ADD will be zero extended to Xmode before underlying code generation. The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_expand_usadd): Zero extend the second operand of usadd as the first operand does. * config/riscv/riscv.md (usadd3): Allow imm operand for scalar usadd pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_u_add-11.c: Make asm check robust. * gcc.target/riscv/sat_u_add-15.c: Ditto. * gcc.target/riscv/sat_u_add-19.c: Ditto. * gcc.target/riscv/sat_u_add-23.c: Ditto. * gcc.target/riscv/sat_u_add-3.c: Ditto. * gcc.target/riscv/sat_u_add-7.c: Ditto. Signed-off-by: Pan Li --- gcc/config/riscv/riscv.cc | 2 +- gcc/config/riscv/riscv.md | 4 ++-- gcc/testsuite/gcc.target/riscv/sat_u_add-11.c | 2 +- gcc/testsuite/gcc.target/riscv/sat_u_add-15.c | 2 +- gcc/testsuite/gcc.target/riscv/sat_u_add-19.c | 2 +- gcc/testsuite/gcc.target/riscv/sat_u_add-23.c | 2 +- gcc/testsuite/gcc.target/riscv/sat_u_add-3.c | 2 +- gcc/testsuite/gcc.target/riscv/sat_u_add-7.c | 2 +- 8 files changed, 9 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index d03e51f3a68..4061d2372b4 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -11970,7 +11970,7 @@ riscv_expand_usadd (rtx dest, rtx x, rtx y) rtx xmode_sum = gen_reg_rtx (Xmode); rtx xmode_lt = gen_reg_rtx (Xmode); rtx xmode_x = riscv_gen_zero_extend_rtx (x, mode); - rtx xmode_y = gen_lowpart (Xmode, y); + rtx xmode_y = riscv_gen_zero_extend_rtx (y, mode); rtx xmode_dest = gen_reg_rtx (Xmode); /* Step-1: sum = x + y */ diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 3289ed2155a..4b0be43f436 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -4358,8 +4358,8 @@ (define_insn_and_split "" (define_expand "usadd3" [(match_operand:ANYI 0 "register_operand") - (match_operand:ANYI 1 "register_operand") - (match_operand:ANYI 2 "register_operand")] + (match_operand:ANYI 1 "reg_or_int_operand") + (match_operand:ANYI 2 "reg_or_int_operand")] "" { riscv_expand_usadd (operands[0], operands[1], operands[2]); diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-11.c index e248aeafa8e..bd830ececad 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_add-11.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-11.c @@ -8,7 +8,7 @@ ** sat_u_add_uint32_t_fmt_3: ** slli\s+[atx][0-9]+,\s*a0,\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a0,\s*a1 +** add\s+[atx][0-9]+,\s*a[01],\s*a[01] ** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 ** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-15.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-15.c index bb8b991a84e..de615a6225e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_add-15.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-15.c @@ -8,7 +8,7 @@ ** sat_u_add_uint32_t_fmt_4: ** slli\s+[atx][0-9]+,\s*a0,\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a0,\s*a1 +** add\s+[atx][0-9]+,\s*a[01],\s*a[01] ** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 ** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-19.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-19.c index 7e4ae12f2f5..2b793e2f8fd 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_add-19.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-19.c @@ -8,7 +8,7 @@ ** sat_u_add_uint32_t_fmt_5: ** slli\s+[atx][0-9]+,\s*a0,\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a0,\s*a1 +** add\s+[atx][0-9]+,\s*a[01],\s*a[01] ** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 ** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-23.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-23.c index 49bbb74a401..5de086e1138 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_add-23.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-23.c @@ -8,7 +8,7 @@ ** sat_u_add_uint32_t_fmt_6: ** slli\s+[atx][0-9]+,\s*a0,\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a0,\s*a1 +** add\s+[atx][0-9]+,\s*a[01],\s*a[01] ** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 ** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-3.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-3.c index cd15dc96450..bd7ccb2a8c7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_add-3.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-3.c @@ -8,7 +8,7 @@ ** sat_u_add_uint32_t_fmt_1: ** slli\s+[atx][0-9]+,\s*a0,\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a0,\s*a1 +** add\s+[atx][0-9]+,\s*a[01],\s*a[01] ** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 ** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-7.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-7.c index a0b79b15ac4..496d5cfbe81 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_add-7.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-7.c @@ -8,7 +8,7 @@ ** sat_u_add_uint32_t_fmt_2: ** slli\s+[atx][0-9]+,\s*a0,\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a0,\s*a1 +** add\s+[atx][0-9]+,\s*a[01],\s*a[01] ** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 ** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+