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X-CSE-ConnectionGUID: TnF7O47iQOO5qeqMdzcvMw== X-CSE-MsgGUID: K/wws9+NSGOlJCMTYlZiqA== X-IronPort-AV: E=McAfee;i="6700,10204,11182"; a="46335237" X-IronPort-AV: E=Sophos;i="6.10,195,1719903600"; d="scan'208";a="46335237" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Sep 2024 22:53:32 -0700 X-CSE-ConnectionGUID: VuLcDoRiR6GccgT1N+zFbg== X-CSE-MsgGUID: 3bPbif3tS0+eUSWBqKtQyw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,195,1719903600"; d="scan'208";a="69297450" Received: from panli.sh.intel.com ([10.239.154.73]) by orviesa003.jf.intel.com with ESMTP; 01 Sep 2024 22:53:30 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, Tamar.Christina@arm.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 2/2] Match: Add int type fits check for form 2 of .SAT_SUB imm operand Date: Mon, 2 Sep 2024 13:52:45 +0800 Message-ID: <20240902055245.3244978-2-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240902055245.3244978-1-pan2.li@intel.com> References: <20240902055245.3244978-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch would like to add strict check for imm operand of .SAT_SUB matching. We have no type checking for imm operand in previous, which may result in unexpected IL to be catched by .SAT_SUB pattern. We leverage the int_fits_type_p here to make sure the imm operand is a int type fits the result type of the .SAT_SUB. For example: Fits uint8_t: uint8_t a; uint8_t sum = .SAT_SUB (a, 12); uint8_t sum = .SAT_SUB (a, 12u); uint8_t sum = .SAT_SUB (a, 126u); uint8_t sum = .SAT_SUB (a, 128u); uint8_t sum = .SAT_SUB (a, 228); uint8_t sum = .SAT_SUB (a, 223u); Not fits uint8_t: uint8_t a; uint8_t sum = .SAT_SUB (a, -1); uint8_t sum = .SAT_SUB (a, 256u); uint8_t sum = .SAT_SUB (a, 257); The below test suite are passed for this patch: * The rv64gcv fully regression test. * The x86 bootstrap test. * The x86 fully regression test. gcc/ChangeLog: * match.pd: Add int_fits_type_p check for .SAT_SUB imm operand. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add test helper macros. * gcc.target/riscv/sat_u_add_imm_type_check-57.c: New test. * gcc.target/riscv/sat_u_add_imm_type_check-58.c: New test. * gcc.target/riscv/sat_u_add_imm_type_check-59.c: New test. * gcc.target/riscv/sat_u_add_imm_type_check-60.c: New test. Signed-off-by: Pan Li --- gcc/match.pd | 2 +- gcc/testsuite/gcc.target/riscv/sat_arith.h | 14 ++++++++++ .../riscv/sat_u_add_imm_type_check-57.c | 18 +++++++++++++ .../riscv/sat_u_add_imm_type_check-58.c | 27 +++++++++++++++++++ .../riscv/sat_u_add_imm_type_check-59.c | 18 +++++++++++++ .../riscv/sat_u_add_imm_type_check-60.c | 27 +++++++++++++++++++ 6 files changed, 105 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-57.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-58.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-59.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-60.c diff --git a/gcc/match.pd b/gcc/match.pd index 45e0cc4a54f..6c54f0502eb 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -3288,7 +3288,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) (match (unsigned_integer_sat_sub @0 @1) (plus (max @0 INTEGER_CST@1) INTEGER_CST@2) (if (INTEGRAL_TYPE_P (type) && TYPE_UNSIGNED (type) - && types_match (type, @1)) + && types_match (type, @1) && int_fits_type_p (@1, type)) (with { unsigned precision = TYPE_PRECISION (type); diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h index 75f48b4b760..4d11b6dcf3b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h @@ -281,6 +281,20 @@ sat_u_sub_imm_type_check##_##INDEX##_##T##_fmt_2 (T y) \ return IMM > y ? IMM - y : 0; \ } +#define DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3(INDEX, T, IMM) \ +T __attribute__((noinline)) \ +sat_u_sub_imm_type_check##_##INDEX##_##T##_fmt_3 (T x) \ +{ \ + return x >= IMM ? x - IMM : 0; \ +} + +#define DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4(INDEX, T, IMM) \ +T __attribute__((noinline)) \ +sat_u_sub_imm_type_check##_##INDEX##_##T##_fmt_4 (T x) \ +{ \ + return x > IMM ? x - IMM : 0; \ +} + /******************************************************************************/ /* Saturation Truncate (unsigned and signed) */ /******************************************************************************/ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-57.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-57.c new file mode 100644 index 00000000000..1b193bcfb26 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-57.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "sat_arith.h" + +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (0, uint8_t, -43) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (1, uint8_t, 269) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (2, uint8_t, 369u) + +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (3, uint16_t, -4) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (4, uint16_t, 65579) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (5, uint16_t, 65679u) + +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (6, uint32_t, -62l) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (7, uint32_t, 6294967342ll) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (8, uint32_t, 4394967342ull) + +/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-58.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-58.c new file mode 100644 index 00000000000..b7dc71b42ee --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-58.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "sat_arith.h" + +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (0, uint8_t, 123u) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (1, uint8_t, 9) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (2, uint8_t, 129) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (3, uint8_t, 234u) + +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (4, uint16_t, 32763u) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (5, uint16_t, 65532u) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (6, uint16_t, 52767) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (7, uint16_t, 9) + +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (8, uint32_t, 4294967293u) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (9, uint32_t, 2147483944) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (10, uint32_t, 4294967142ll) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (11, uint32_t, 2147483644u) + +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (12, uint64_t, -6232) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (13, uint64_t, 6293232) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (14, uint64_t, 576460752303483482) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (15, uint64_t, 576460752303423482u) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_3 (16, uint64_t, 976460752303483482u) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 34 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-59.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-59.c new file mode 100644 index 00000000000..4f2fb307949 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-59.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "sat_arith.h" + +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (0, uint8_t, -43) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (1, uint8_t, 269) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (2, uint8_t, 369u) + +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (3, uint16_t, -4) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (4, uint16_t, 65579) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (5, uint16_t, 65679u) + +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (6, uint32_t, -62l) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (7, uint32_t, 4294967342ll) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (8, uint32_t, 4394967342ull) + +/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-60.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-60.c new file mode 100644 index 00000000000..b32e69ea859 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-60.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "sat_arith.h" + +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (0, uint8_t, 126u) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (1, uint8_t, 9) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (2, uint8_t, 129) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (3, uint8_t, 253u) + +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (4, uint16_t, 32767u) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (5, uint16_t, 65532u) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (6, uint16_t, 52767) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (7, uint16_t, 9) + +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (8, uint32_t, 4294967293u) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (9, uint32_t, 2147483944) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (10, uint32_t, 4294967042ll) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (11, uint32_t, 2147483644u) + +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (12, uint64_t, -6232) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (13, uint64_t, 6293232) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (14, uint64_t, 576460752303483482) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (15, uint64_t, 576460752303423482u) +DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_4 (16, uint64_t, 976460752303483482u) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 34 "expand" } } */