From patchwork Sun Aug 25 06:18:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1976473 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=ktDMKDsi; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ws3Yt4CjFz1yg5 for ; Sun, 25 Aug 2024 16:19:45 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C46173861818 for ; Sun, 25 Aug 2024 06:19:42 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by sourceware.org (Postfix) with ESMTPS id 62A283858410 for ; Sun, 25 Aug 2024 06:19:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 62A283858410 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 62A283858410 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724566753; cv=none; b=IkONj1bRFsBVZNxuucQKaw2+uDvcVpPLLeQI/m5bqpPePzOr5UCG0eseZoChlFp1dg9RTyIFw5n/lPrgBBHvUwb9Ssl1uKB6WYcX+RKNhsVsEEOYbuzN1XUr/gLKvccN8SxLPgH+JvLr4r1ABTQrW+ZHij8JFdw+tALyU4xG+Vs= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724566753; c=relaxed/simple; bh=QwBN61XOpkco5wZNM6gXJA4tgbBfNNzVR1Gg/riiqlU=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=Lw2gZIGRvlgf/bdCQhse3bPxxiMg5dF9hBDdG97Tpt34TVWduEl4CEgjbweDrRL8DmzD0gNsXh8iBkoRgNI8isXkTDTDAPnAQCPkZZucS+6zX0a3FVoGYojrluAs+fZapfHfc8MEbAspunkUgYCx4TuNuNiUiRYpWH52PZTTlk8= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724566750; x=1756102750; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=QwBN61XOpkco5wZNM6gXJA4tgbBfNNzVR1Gg/riiqlU=; b=ktDMKDsiNtOScXFUtSKpz8xs2Ir0dI6cQAbY5F0k+5/bOGliJ0p4mrcy GiM6x+3uxSuQN+gFFqJc2/EBtBjo0VPA/2ydyIjo1ksv5WrhEl5k0TJkM rai8/Tzs1GmmpPGWI4TpgcUBdnxfV0yEyblRcZGhI8Qsi2nsYsR/BUdXY wmsehW9fUIFyC6MoqOofRAeoDpSsZg0cD8Hl61EYCT4JOk08S+tZPVbBc S/UunJ8p8S4FLAQvopxU4G5chftWLYZRlfS/eRSsknxLxfsj+/JlxHzt7 cnc6fn7+CO5q9dYnnecKO6LvtCuNzmIlj9mU/dqym4FjydfjgZQFqyZqm A==; X-CSE-ConnectionGUID: 3hGiOabdRGGwCVh1k7M7uw== X-CSE-MsgGUID: c7LzHI6dQt2irTDKU4M6jw== X-IronPort-AV: E=McAfee;i="6700,10204,11173"; a="25896323" X-IronPort-AV: E=Sophos;i="6.10,174,1719903600"; d="scan'208";a="25896323" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Aug 2024 23:19:09 -0700 X-CSE-ConnectionGUID: kUNCTYtTQvaFqm0IWpWD7Q== X-CSE-MsgGUID: 5Eay0T1HTLyEOyB5mVo5qQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,174,1719903600"; d="scan'208";a="62247538" Received: from panli.sh.intel.com ([10.239.154.73]) by fmviesa009.fm.intel.com with ESMTP; 24 Aug 2024 23:19:07 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 4 Date: Sun, 25 Aug 2024 14:18:34 +0800 Message-ID: <20240825061835.1931708-1-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch would like to add test cases for the unsigned scalar quad and oct .SAT_TRUNC form 4. Aka: Form 4: #define DEF_SAT_U_TRUNC_FMT_4(NT, WT) \ NT __attribute__((noinline)) \ sat_u_trunc_##WT##_to_##NT##_fmt_4 (WT x) \ { \ bool not_overflow = x <= (WT)(NT)(-1); \ return ((NT)x) | (NT)((NT)not_overflow - 1); \ } The below test is passed for this patch. * The rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add test helper macros. * gcc.target/riscv/sat_u_trunc-19.c: New test. * gcc.target/riscv/sat_u_trunc-20.c: New test. * gcc.target/riscv/sat_u_trunc-21.c: New test. * gcc.target/riscv/sat_u_trunc-22.c: New test. * gcc.target/riscv/sat_u_trunc-23.c: New test. * gcc.target/riscv/sat_u_trunc-24.c: New test. * gcc.target/riscv/sat_u_trunc-run-19.c: New test. * gcc.target/riscv/sat_u_trunc-run-20.c: New test. * gcc.target/riscv/sat_u_trunc-run-21.c: New test. * gcc.target/riscv/sat_u_trunc-run-22.c: New test. * gcc.target/riscv/sat_u_trunc-run-23.c: New test. * gcc.target/riscv/sat_u_trunc-run-24.c: New test. Signed-off-by: Pan Li --- gcc/testsuite/gcc.target/riscv/sat_arith.h | 12 +++++++++++ .../gcc.target/riscv/sat_u_trunc-19.c | 17 ++++++++++++++++ .../gcc.target/riscv/sat_u_trunc-20.c | 20 +++++++++++++++++++ .../gcc.target/riscv/sat_u_trunc-21.c | 19 ++++++++++++++++++ .../gcc.target/riscv/sat_u_trunc-22.c | 17 ++++++++++++++++ .../gcc.target/riscv/sat_u_trunc-23.c | 17 ++++++++++++++++ .../gcc.target/riscv/sat_u_trunc-24.c | 20 +++++++++++++++++++ .../gcc.target/riscv/sat_u_trunc-run-19.c | 16 +++++++++++++++ .../gcc.target/riscv/sat_u_trunc-run-20.c | 16 +++++++++++++++ .../gcc.target/riscv/sat_u_trunc-run-21.c | 16 +++++++++++++++ .../gcc.target/riscv/sat_u_trunc-run-22.c | 16 +++++++++++++++ .../gcc.target/riscv/sat_u_trunc-run-23.c | 16 +++++++++++++++ .../gcc.target/riscv/sat_u_trunc-run-24.c | 16 +++++++++++++++ 13 files changed, 218 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-19.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-20.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-21.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-22.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-23.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-24.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-19.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-20.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-21.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-22.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-23.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-24.c diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h index 91853b60f59..229e1f0a5cd 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h @@ -245,6 +245,15 @@ sat_u_trunc_##WT##_to_##NT##_fmt_3 (WT x) \ } #define DEF_SAT_U_TRUNC_FMT_3_WRAP(NT, WT) DEF_SAT_U_TRUNC_FMT_3(NT, WT) +#define DEF_SAT_U_TRUNC_FMT_4(NT, WT) \ +NT __attribute__((noinline)) \ +sat_u_trunc_##WT##_to_##NT##_fmt_4 (WT x) \ +{ \ + bool not_overflow = x <= (WT)(NT)(-1); \ + return ((NT)x) | (NT)((NT)not_overflow - 1); \ +} +#define DEF_SAT_U_TRUNC_FMT_4_WRAP(NT, WT) DEF_SAT_U_TRUNC_FMT_4(NT, WT) + #define RUN_SAT_U_TRUNC_FMT_1(NT, WT, x) sat_u_trunc_##WT##_to_##NT##_fmt_1 (x) #define RUN_SAT_U_TRUNC_FMT_1_WRAP(NT, WT, x) RUN_SAT_U_TRUNC_FMT_1(NT, WT, x) @@ -254,4 +263,7 @@ sat_u_trunc_##WT##_to_##NT##_fmt_3 (WT x) \ #define RUN_SAT_U_TRUNC_FMT_3(NT, WT, x) sat_u_trunc_##WT##_to_##NT##_fmt_3 (x) #define RUN_SAT_U_TRUNC_FMT_3_WRAP(NT, WT, x) RUN_SAT_U_TRUNC_FMT_3(NT, WT, x) +#define RUN_SAT_U_TRUNC_FMT_4(NT, WT, x) sat_u_trunc_##WT##_to_##NT##_fmt_4 (x) +#define RUN_SAT_U_TRUNC_FMT_4_WRAP(NT, WT, x) RUN_SAT_U_TRUNC_FMT_4(NT, WT, x) + #endif diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-19.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-19.c new file mode 100644 index 00000000000..e61faffbbc6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-19.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_trunc_uint16_t_to_uint8_t_fmt_4: +** sltiu\s+[atx][0-9]+,\s*a0,\s*255 +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff +** ret +*/ +DEF_SAT_U_TRUNC_FMT_4(uint8_t, uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-20.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-20.c new file mode 100644 index 00000000000..708b2b2394d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-20.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_trunc_uint32_t_to_uint16_t_fmt_4: +** li\s+[atx][0-9]+,\s*65536 +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** slli\s+a0,\s*a0,\s*48 +** srli\s+a0,\s*a0,\s*48 +** ret +*/ +DEF_SAT_U_TRUNC_FMT_4(uint16_t, uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-21.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-21.c new file mode 100644 index 00000000000..e522a90ecdb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-21.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_trunc_uint64_t_to_uint32_t_fmt_4: +** li\s+[atx][0-9]+,\s*-1 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 +** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** sext.w\s+a0,\s*a0 +** ret +*/ +DEF_SAT_U_TRUNC_FMT_4(uint32_t, uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-22.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-22.c new file mode 100644 index 00000000000..db75cd0c6dc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-22.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_trunc_uint32_t_to_uint8_t_fmt_4: +** sltiu\s+[atx][0-9]+,\s*a0,\s*255 +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff +** ret +*/ +DEF_SAT_U_TRUNC_FMT_4(uint8_t, uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-23.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-23.c new file mode 100644 index 00000000000..7acc6587304 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-23.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_trunc_uint64_t_to_uint8_t_fmt_4: +** sltiu\s+[atx][0-9]+,\s*a0,\s*255 +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff +** ret +*/ +DEF_SAT_U_TRUNC_FMT_4(uint8_t, uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-24.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-24.c new file mode 100644 index 00000000000..32952f5b283 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-24.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_trunc_uint64_t_to_uint16_t_fmt_4: +** li\s+[atx][0-9]+,\s*65536 +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** slli\s+a0,\s*a0,\s*48 +** srli\s+a0,\s*a0,\s*48 +** ret +*/ +DEF_SAT_U_TRUNC_FMT_4(uint16_t, uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-19.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-19.c new file mode 100644 index 00000000000..7f52283fbeb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-19.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint8_t +#define T2 uint16_t + +DEF_SAT_U_TRUNC_FMT_4_WRAP(T1, T2) + +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define RUN_UNARY(x) RUN_SAT_U_TRUNC_FMT_4_WRAP(T1, T2, x) + +#include "scalar_sat_unary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-20.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-20.c new file mode 100644 index 00000000000..ee13f0abb9b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-20.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint16_t +#define T2 uint32_t + +DEF_SAT_U_TRUNC_FMT_4_WRAP(T1, T2) + +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define RUN_UNARY(x) RUN_SAT_U_TRUNC_FMT_4_WRAP(T1, T2, x) + +#include "scalar_sat_unary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-21.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-21.c new file mode 100644 index 00000000000..a1b8a5f19d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-21.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint32_t +#define T2 uint64_t + +DEF_SAT_U_TRUNC_FMT_4_WRAP(T1, T2) + +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define RUN_UNARY(x) RUN_SAT_U_TRUNC_FMT_4_WRAP(T1, T2, x) + +#include "scalar_sat_unary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-22.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-22.c new file mode 100644 index 00000000000..f056bd42e91 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-22.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint8_t +#define T2 uint32_t + +DEF_SAT_U_TRUNC_FMT_4_WRAP(T1, T2) + +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define RUN_UNARY(x) RUN_SAT_U_TRUNC_FMT_4_WRAP(T1, T2, x) + +#include "scalar_sat_unary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-23.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-23.c new file mode 100644 index 00000000000..96c06ebcd12 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-23.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint8_t +#define T2 uint64_t + +DEF_SAT_U_TRUNC_FMT_4_WRAP(T1, T2) + +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define RUN_UNARY(x) RUN_SAT_U_TRUNC_FMT_4_WRAP(T1, T2, x) + +#include "scalar_sat_unary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-24.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-24.c new file mode 100644 index 00000000000..1623e521fce --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-24.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint16_t +#define T2 uint64_t + +DEF_SAT_U_TRUNC_FMT_4_WRAP(T1, T2) + +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define RUN_UNARY(x) RUN_SAT_U_TRUNC_FMT_4_WRAP(T1, T2, x) + +#include "scalar_sat_unary.h"